JPS6482831A - Synchronizing pattern multiplexing circuit - Google Patents

Synchronizing pattern multiplexing circuit

Info

Publication number
JPS6482831A
JPS6482831A JP62241428A JP24142887A JPS6482831A JP S6482831 A JPS6482831 A JP S6482831A JP 62241428 A JP62241428 A JP 62241428A JP 24142887 A JP24142887 A JP 24142887A JP S6482831 A JPS6482831 A JP S6482831A
Authority
JP
Japan
Prior art keywords
synchronizing pattern
circuit
transmission system
information
memory circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62241428A
Other languages
Japanese (ja)
Inventor
Kyosuke Dobashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62241428A priority Critical patent/JPS6482831A/en
Publication of JPS6482831A publication Critical patent/JPS6482831A/en
Pending legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To easily obtain a circuit to be able to correspond to the change of a transmission system without fail by supplying designation information prepared from a synchronizing pattern designating circuit and a frame counter and timing information together with the transmission data as address information to a memory circuit. CONSTITUTION:When an operator executes the designation operation of a new transmission system with a console panel accompanying the change of the applied transmission system, designation information CS of a frame synchronizing pattern used with a new transmission system is outputted from a synchronizing pattern designating circuit 7 and supplied to a memory circuit 8. In this condition, when transmitting data SD are inputted, timing information TS to show respective bit positions of the transmission data SD is outputted from a frame counter 2 and supplied to the memory circuit 8, transmission data FSD to multiplex the frame synchronization pattern from a memory area corresponding to the address information displayed by the designation information CS of a synchronizing pattern, the transmission data SD and the timing information TS are read from the memory circuit 8.
JP62241428A 1987-09-25 1987-09-25 Synchronizing pattern multiplexing circuit Pending JPS6482831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62241428A JPS6482831A (en) 1987-09-25 1987-09-25 Synchronizing pattern multiplexing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62241428A JPS6482831A (en) 1987-09-25 1987-09-25 Synchronizing pattern multiplexing circuit

Publications (1)

Publication Number Publication Date
JPS6482831A true JPS6482831A (en) 1989-03-28

Family

ID=17074153

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62241428A Pending JPS6482831A (en) 1987-09-25 1987-09-25 Synchronizing pattern multiplexing circuit

Country Status (1)

Country Link
JP (1) JPS6482831A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007184790A (en) * 2006-01-06 2007-07-19 Canon Inc Data transmitting device, data receiving device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007184790A (en) * 2006-01-06 2007-07-19 Canon Inc Data transmitting device, data receiving device

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