JPS6482864A - Control circuit for video memory - Google Patents

Control circuit for video memory

Info

Publication number
JPS6482864A
JPS6482864A JP24162087A JP24162087A JPS6482864A JP S6482864 A JPS6482864 A JP S6482864A JP 24162087 A JP24162087 A JP 24162087A JP 24162087 A JP24162087 A JP 24162087A JP S6482864 A JPS6482864 A JP S6482864A
Authority
JP
Japan
Prior art keywords
channel
signal
generated
picture
screen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24162087A
Other languages
Japanese (ja)
Other versions
JP2834732B2 (en
Inventor
Tomoshi Tanaka
Hiroaki Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62241620A priority Critical patent/JP2834732B2/en
Publication of JPS6482864A publication Critical patent/JPS6482864A/en
Application granted granted Critical
Publication of JP2834732B2 publication Critical patent/JP2834732B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Studio Circuits (AREA)

Abstract

PURPOSE:To prevent the disorder of an image from being generated on a screen at the time of switching by stopping write to a memory beforehand, when a video signal written in the memory is switched, and thereafter, reading out repeatedly the same contents for a prescribed period. CONSTITUTION:When a picture-in-picture processing is being executed, and a video signal from a tuner 1 is selected for slave picture plane use, only a channel switching signal from a timing control circuit 19 becomes effective. In this state, a still picture instructing signal S rises at a timing of a vertical synchronizing signal of the next slave screen in which a channel switching signal CH from a channel selection switching instruction circuit 16 or a sequential channel selection means 17 has been generated. Accordingly, as for a memory 9, only a read-out operation is executed. Subsequently, at a timing of a second vertical synchronizing signal, a channel switching signal Tu is outputted, and a channel selection channel is changed. In this case, a video signal of an old channel is read out repeatedly, therefore, no disorder is generated on a screen of a TV receiver.
JP62241620A 1987-09-25 1987-09-25 Video memory control circuit Expired - Lifetime JP2834732B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62241620A JP2834732B2 (en) 1987-09-25 1987-09-25 Video memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62241620A JP2834732B2 (en) 1987-09-25 1987-09-25 Video memory control circuit

Publications (2)

Publication Number Publication Date
JPS6482864A true JPS6482864A (en) 1989-03-28
JP2834732B2 JP2834732B2 (en) 1998-12-14

Family

ID=17077034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62241620A Expired - Lifetime JP2834732B2 (en) 1987-09-25 1987-09-25 Video memory control circuit

Country Status (1)

Country Link
JP (1) JP2834732B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0342975A (en) * 1989-07-03 1991-02-25 Thomson Consumer Electron Inc Sample data processer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55161475A (en) * 1979-06-04 1980-12-16 Fujitsu General Ltd Squelch circuit of television receiver
JPS62145972A (en) * 1985-12-19 1987-06-30 Mitsubishi Electric Corp Television receiver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55161475A (en) * 1979-06-04 1980-12-16 Fujitsu General Ltd Squelch circuit of television receiver
JPS62145972A (en) * 1985-12-19 1987-06-30 Mitsubishi Electric Corp Television receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0342975A (en) * 1989-07-03 1991-02-25 Thomson Consumer Electron Inc Sample data processer

Also Published As

Publication number Publication date
JP2834732B2 (en) 1998-12-14

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term