JPS648380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplexed arithmetic processing device, and is particularly suitable for a system in which the same arithmetic processing is performed by a plurality of processing devices and is required to output highly reliable arithmetic results. , relates to a multiplexed arithmetic processing device.

In recent years, online use of information processing devices has become popular, and demands for system reliability and real-time performance are increasing. For example, for plant control devices, instead of conventional control devices consisting only of hardware, computers (hereinafter referred to as CPUs)
More advanced control is achieved using a control device that utilizes .

In order to improve the reliability of the system, control devices using such CPUs often employ a multiplexed arithmetic processing system in which a plurality of control devices with the same function are installed. This multiple system control device performs the same processing on the same input signal under the same conditions. Therefore, the same output is obtained from the plurality of CPUs, and after confirming the coincidence, the output is output to the controlled object as an output signal of the multi-system control device.

However, in such a dual-and method,
There may be a slight time lag when the CPU reads the input signal, or a slight deviation in the base clock may cause the outputs of multiple CPUs to not match, even though the CPU processing is normal. In other words, if the synchronization of multiple CPUs is broken, signals with the same content as output signals may become shorter in terms of timing, or the outputs may not match, making it impossible to perform a predetermined operation.

For this reason, there was a tendency to abandon the dual-and system and adopt the duplex system (working system and standby system). However, there are systems that require extremely high reliability and real-time performance, and fields where there is an extremely strong desire to configure malfunction prevention systems using CPUs.

Conventionally, in this field, synchronized clock pulses were supplied to multiple CPUs because it was necessary to match the content and input timing of input data to multiple CPUs in order to ensure that the output information of multiple CPUs matched. However, methods were used in which the same logical information was processed for each clock, and methods were used to synchronize the processing of a group of CPUs using a special input control device. CPUs that configure a multiplex system like this
Complex and large-scale support hardware was required to ensure that the input data of the groups matched and to match the input timing. However, when this method is applied to small CPUs, especially systems with small CPUs such as microcomputers, the special equipment for synchronization becomes relatively large compared to the CPU, and reliability and economy are affected. This results in sexual inconvenience. In particular, in terms of reliability, the reliability of the special device for synchronization is worse than that of the CPU, and this has caused essential problems such as the point of having the CPU as a multi-system as a whole is completely lost. Therefore, in this field, the emergence of a synchronization system that minimizes common hardware has become an essential element.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplexed arithmetic processing device that can eliminate the drawbacks of the prior art described above, effectively improve reliability, and simplify the configuration.

In order to achieve this objective, in the present invention,
An information transmission means is provided between each multiplexed processing device, and this is used to send and receive commands, making it possible to match the input data acquisition time and the output timing, and furthermore, it is possible for each computer to By sending a down signal to each other to notify each other that the computer is down, it is possible to speed up the calculation processing time of the remaining normal computers, and when the entire system is normal, this down signal can be used to detect a failure in the information transmission means. It is characterized by what it did.

Hereinafter, the present invention will be explained in detail with reference to the embodiment shown in FIG. This example is a case of a duplex configuration, and
The A-system and B-system CPUs 6 and 7 are connected by a bus 10 as an information transmission means and a signal line 11 for mutually informing each other of down signals. Input data 1 is input to CPUs 6 and 7 (internal clocks 8 and 9).
(operation)) to produce outputs 2 and 3, and an AND circuit 4 detects this coincidence to produce output data 5. The feature of this dual and system configuration is that as common hardware between the two CPUs,
Only the bus 10 and its monitoring means, the signal line 11, are present. And during normal times,
The duplexing device synchronizes data input/output and arithmetic processing with the outside using only the bus 10, and the signal line 11 is activated in the event of a failure, and its operation will be explained below.

FIG. 2 is a flowchart of the processing operations of the A-system and B-system CPUs 6 and 7 when both are normal. In the figure, first, the CPU 6 starts a program at regular intervals by a timer (not shown), and sends a command signal C1 to the CPU 7 via the bus 10. The CPU 7 receives this command C1, starts the program, and immediately returns a response signal R1 to the CPU 6 after receiving the command C1. via bus 10
Since the transmission time from the CPU 7 to the CPU 6 can be known in advance, after transmitting the response R1, the CPU 7 performs external data input processing after the transmission time.
On the other hand, since the CPU 6 performs data input processing immediately after receiving the response R1, this simple command transmission and reception makes it possible to match the input timing of external data. Subsequently, each of the CPUs 6 and 7 performs arithmetic processing using this same input data, and when the CPU 6 completes the arithmetic processing, it transmits the command signal C2 again via the bus 10.
The CPU 7 finishes the arithmetic processing and executes the command C2.
When it receives the response signal R2, it sends a response signal R2 to the CPU 6, indicating that the CPU 7 has finished the calculation process.
Notify CPU6. After transmitting the response signal R2 in the same manner as described above, the CPU 7 waits for the required transmission time and then performs the data output process, while the CPU 6 immediately performs the data output process after receiving the response R2. Therefore, since the same data 2 and 3 with synchronized calculations are output to the outside, the same data is input from both CPUs at the same time to the output data matching circuit (AND circuit 4) in Fig. 1, and the logic Even if the product is calculated, no matching mismatch will occur. In this way, when both systems are normal, the input and output of the redundant system can be synchronized by simply transmitting and receiving commands and responses using only the bus 10.

Next, if one of the CPUs, for example CPU7, goes down, according to the flowchart as shown in Figure 2, CPU6 waits for a certain period of time to receive response R1 from CPU7 after sending command C1, and then R1 is not received. CPU7 due to failure
Recognize obstacles. Further, the CPU 6 sends the command C2 to the CPU 7 even after the calculation is completed, and outputs the data after confirming that there is no reply R2. Because of this long waiting time, if one of them fails, there will be a large delay in calculation time, which will not only lengthen the calculation cycle, but may also cause trouble to the outside.

The signal line 11 is provided to speed up processing when one system (partial) fails, and has a function of notifying the other CPU of a failure in its own system.
For this purpose, the RUN contact itself of the hardware of each CPU may be sent via the signal line 11, or the corresponding signal may be created using software.

Figure 3 shows when this signal line 11 is also used.
This shows a flowchart when CPU7 fails.
In the figure, the CPU 6 first determines the state of the other party's CPU 7 obtained using the signal line 11, and
If it is confirmed that the CPU 7 is down, process A1 is performed. In other words, without sending or receiving commands,
Immediately transitions to normal CPU single-system self-running mode,
It performs processing such as data input, arithmetic processing, and data output, and aims to speed up processing. Note that this judgment process is performed every time the CPU 6 program is started, so if the CPU 7 returns to normal mode, the signal line 11 allows the other CPU 7 to
The recovery can be confirmed, and the process shown on the right side of Figure 3 can be confirmed.
A smooth transition can be made to A0, that is, the operation synchronization mode when both systems are normal (same as in Fig. 2).

In case of a failure in the CPU 6, the CPU 7 periodically checks the signal line 11, and if it is determined that the CPU 6 has failed, the same process as process A1 in FIG. 3 can be performed.

Also, by using the signal of signal line 11,
Faults in the bus 10 that governs synchronization can be discovered. The method is shown in FIG.

As explained in FIG. 2, in the dual-system arithmetic synchronization system, the CPU 6 first sends the command C1 to the CPU 7. If the response R1 can be received, normal processing can be continued, but if R1 cannot be received even after waiting for a certain period of time, check whether the cause is due to an abnormality in the other CPU.
It is difficult to determine whether this is due to a disability. Therefore, the status of the other CPU is determined using the signal line 11, and if the other CPU is running normally, it can be determined that the failure is caused by the bus 10.

As is clear from the above embodiments, according to the present invention, only a small amount of common hardware is added to each CPU, and the arithmetic processing of each CPU is not synchronized. High-speed processing can be achieved using the normal CPU, and failures in the information transmission path as a means of synchronization can also be automatically detected. Moreover, even if there are two or more CPUs, it is easy to implement, and has the effect of realizing a highly reliable multiplexed processing system.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an embodiment of the device of the present invention, Fig. 2 is an operation flowchart when both CPUs are normal, Fig. 3 is an operation flowchart when one CPU is down, and Fig. 4 is an information 7 is a flowchart showing a procedure for recognizing a failure in a transmission means. 1... Input data, 2, 3... Operation result data, 4... AND gate, 5... Output, 6, 7...
...CPU, 10...Bus, 11...Signal line.

Claims (1)

[Scope of Claims] 1. In a multiplexed arithmetic processing device configured to perform arithmetic processing on the same input data by a plurality of processing means and output the results after matching each output, the plurality of processing means An information transmission means is provided for transmitting commands and response signals therebetween, and each processing means is used to detect coincidence at the time when one input data is taken into each processing means and after the input data is subjected to arithmetic processing. The processing means is configured to synchronize the operations at each point in time by transmitting and receiving the command and response signals between the respective processing means prior to the point in time when results are retrieved from the processing means, and
A signal line is provided between each processing means to notify each other of a malfunction in its own processing means, and the commands and responses are transmitted and received between the processing means recognized as having a malfunction via the signal line. 1. A multiplexed arithmetic processing device, characterized in that it is configured to output arithmetic processing results by matching only normal processing means. 2. If the two processing means do not notify each other of a failure via the signal line, and the command and response signals cannot be sent and received between the two processing means, the above two processing The multiplexing arithmetic processing device according to claim 1, characterized in that it is configured to determine that the information transmission means between the means has failed.