JPS6484321A - Precharging type bus device - Google Patents

Precharging type bus device

Info

Publication number
JPS6484321A
JPS6484321A JP24231987A JP24231987A JPS6484321A JP S6484321 A JPS6484321 A JP S6484321A JP 24231987 A JP24231987 A JP 24231987A JP 24231987 A JP24231987 A JP 24231987A JP S6484321 A JPS6484321 A JP S6484321A
Authority
JP
Japan
Prior art keywords
precharging
signal
bus
nand
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24231987A
Other languages
Japanese (ja)
Inventor
Shinkou Yamako
Yuichi Nakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP24231987A priority Critical patent/JPS6484321A/en
Publication of JPS6484321A publication Critical patent/JPS6484321A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To rap;idly determine a data output by providing the titled device with a precharging control means for turning off a precharging means when a bus is set up to one potential value. CONSTITUTION:The state of a bus signal is inverted by an inverter 14, the inverted signal is supplied to one input of a NAND 15 and a precharging signal is supplied to the other input to turn on and off a precharging p-channel transistor (TR) 1. Namely, when a bus 4 is charged and turned to an H state, an 'L' signal is inputted to the NAND 15, so that the H signal is inputted to TR 1, and the TR 1 is turned off. Thereby, precharging current does not flow until a logical determination period. Consequently, a time required for the determination of the output to the bus 4 can be shortened.
JP24231987A 1987-09-25 1987-09-25 Precharging type bus device Pending JPS6484321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24231987A JPS6484321A (en) 1987-09-25 1987-09-25 Precharging type bus device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24231987A JPS6484321A (en) 1987-09-25 1987-09-25 Precharging type bus device

Publications (1)

Publication Number Publication Date
JPS6484321A true JPS6484321A (en) 1989-03-29

Family

ID=17087439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24231987A Pending JPS6484321A (en) 1987-09-25 1987-09-25 Precharging type bus device

Country Status (1)

Country Link
JP (1) JPS6484321A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05108562A (en) * 1991-10-15 1993-04-30 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05108562A (en) * 1991-10-15 1993-04-30 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device

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