JPS6484341A - In-circuit emulator - Google Patents

In-circuit emulator

Info

Publication number
JPS6484341A
JPS6484341A JP62243169A JP24316987A JPS6484341A JP S6484341 A JPS6484341 A JP S6484341A JP 62243169 A JP62243169 A JP 62243169A JP 24316987 A JP24316987 A JP 24316987A JP S6484341 A JPS6484341 A JP S6484341A
Authority
JP
Japan
Prior art keywords
memory
program
bank
address
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62243169A
Other languages
Japanese (ja)
Inventor
Yasuyuki Oguma
Toyotaka Ryu
Eiji Teramoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP62243169A priority Critical patent/JPS6484341A/en
Publication of JPS6484341A publication Critical patent/JPS6484341A/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To surely debug a program at real time even when a program is applied to plural memory banks by storing the program in an emulation memory so that each memory bank is stored in each different address. CONSTITUTION:Respective programs stored in respective bank memories in a target memory 29 are stored in respectively different address areas corresponding to respective bank memories out of the address areas in the emulation memory 33 by a mapping circuit 32 and a bank signal detecting circuit 38. Thereby, respective programs stored in the memory 33 are successively read out and debugged. When a break point is inputted to a break point detecting circuit 34, an address value in the memory 33 or 29 corresponding to the address value of the bank memory concerned is detected, and at the time of reading out the program or data existing in the address concerned, program operation is stopped. Consequently, the program can be surely debugged at real time.
JP62243169A 1987-09-28 1987-09-28 In-circuit emulator Pending JPS6484341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62243169A JPS6484341A (en) 1987-09-28 1987-09-28 In-circuit emulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62243169A JPS6484341A (en) 1987-09-28 1987-09-28 In-circuit emulator

Publications (1)

Publication Number Publication Date
JPS6484341A true JPS6484341A (en) 1989-03-29

Family

ID=17099839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62243169A Pending JPS6484341A (en) 1987-09-28 1987-09-28 In-circuit emulator

Country Status (1)

Country Link
JP (1) JPS6484341A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02294741A (en) * 1989-05-09 1990-12-05 Ando Electric Co Ltd Control circuit for emulation memory
JPH02307126A (en) * 1989-05-23 1990-12-20 Yokogawa Electric Corp In-circuit emulator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02294741A (en) * 1989-05-09 1990-12-05 Ando Electric Co Ltd Control circuit for emulation memory
JPH02307126A (en) * 1989-05-23 1990-12-20 Yokogawa Electric Corp In-circuit emulator

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