JPS648439A - Arithmetic circuit for fuzzy control - Google Patents

Arithmetic circuit for fuzzy control

Info

Publication number
JPS648439A
JPS648439A JP62164452A JP16445287A JPS648439A JP S648439 A JPS648439 A JP S648439A JP 62164452 A JP62164452 A JP 62164452A JP 16445287 A JP16445287 A JP 16445287A JP S648439 A JPS648439 A JP S648439A
Authority
JP
Japan
Prior art keywords
data
circuit
digits
comparator
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62164452A
Other languages
Japanese (ja)
Inventor
Haruki Nagao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62164452A priority Critical patent/JPS648439A/en
Publication of JPS648439A publication Critical patent/JPS648439A/en
Pending legal-status Critical Current

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  • Complex Calculations (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

PURPOSE:To reduce the area of a circuit and to speed up a processing by monitoring data on a data bus, executing the arithmetic processing of data and executing operation necessary for fuzzy control in parallel. CONSTITUTION:Two data transferred to a data bus are detected by a monitoring circuit 3 and informed to registers 2a, 2b and a comparator 4. A smaller value is applied to the comparator 4. When data applied from the comparator 4 are A, a line decoder 5 writes the data of (A+1) digits as real data in a storage circuit 7 in a writing mode in response to a control signal 9, and in an operation mode, holds the maximum value of the data and processes the data similarly to the writing mode. A clear circuit 6 turns all digits under the digits selected by the decoder 5 to real values. The storage circuit 7 also holds the data in the circuit 6 in the writing mode in response to the signal 9, and in the operation mode, clears data in the unreal digits of the signal from the circuit 6. An encoder 8 forms binary data based on the most significant value of data obtained from the circuit 7. Thus, high speed processing can be attained.
JP62164452A 1987-06-30 1987-06-30 Arithmetic circuit for fuzzy control Pending JPS648439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62164452A JPS648439A (en) 1987-06-30 1987-06-30 Arithmetic circuit for fuzzy control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164452A JPS648439A (en) 1987-06-30 1987-06-30 Arithmetic circuit for fuzzy control

Publications (1)

Publication Number Publication Date
JPS648439A true JPS648439A (en) 1989-01-12

Family

ID=15793442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164452A Pending JPS648439A (en) 1987-06-30 1987-06-30 Arithmetic circuit for fuzzy control

Country Status (1)

Country Link
JP (1) JPS648439A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6975062B2 (en) 2002-01-17 2005-12-13 Denso Corporation Spark plug with powder filling

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6975062B2 (en) 2002-01-17 2005-12-13 Denso Corporation Spark plug with powder filling

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KRENKE et al. THE USE OF A PROCESS COMPUTER IN AN ENVIRONMENTAL MONITORING SYSTEM