JPS6484931A - Synchronizing multiplexer - Google Patents

Synchronizing multiplexer

Info

Publication number
JPS6484931A
JPS6484931A JP24220787A JP24220787A JPS6484931A JP S6484931 A JPS6484931 A JP S6484931A JP 24220787 A JP24220787 A JP 24220787A JP 24220787 A JP24220787 A JP 24220787A JP S6484931 A JPS6484931 A JP S6484931A
Authority
JP
Japan
Prior art keywords
frame
low order
signal
constitution
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24220787A
Other languages
Japanese (ja)
Inventor
Yoshiki Kamata
Mitsuhiro Tajiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24220787A priority Critical patent/JPS6484931A/en
Publication of JPS6484931A publication Critical patent/JPS6484931A/en
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To obtain a synchronizing multiplexer to synchronizingmultiplex a low order group signal without changing a transmitting speed by changing the attribute of a frame bit added to the low order group signal for the signal. CONSTITUTION:In a case where the frame constitution of two inputted low order group signals CH1 and CH2 and the frame constitution of a synchronized multiple signal are made as shown on a figure, when respective frame bits of the low order, group signals CH1 and CH2 are an F and an F' and an information bit is indicated as an I, respective polarities of the frame pulses of the frame bit F and frame bit F', are set so as to be mutually reverse. In such a way, at a receiving side, a separation into two channels can be executed based on a difference in the frame bits.
JP24220787A 1987-09-25 1987-09-25 Synchronizing multiplexer Pending JPS6484931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24220787A JPS6484931A (en) 1987-09-25 1987-09-25 Synchronizing multiplexer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24220787A JPS6484931A (en) 1987-09-25 1987-09-25 Synchronizing multiplexer

Publications (1)

Publication Number Publication Date
JPS6484931A true JPS6484931A (en) 1989-03-30

Family

ID=17085843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24220787A Pending JPS6484931A (en) 1987-09-25 1987-09-25 Synchronizing multiplexer

Country Status (1)

Country Link
JP (1) JPS6484931A (en)

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