JPS6484942A - Packet buffer control system - Google Patents

Packet buffer control system

Info

Publication number
JPS6484942A
JPS6484942A JP24218387A JP24218387A JPS6484942A JP S6484942 A JPS6484942 A JP S6484942A JP 24218387 A JP24218387 A JP 24218387A JP 24218387 A JP24218387 A JP 24218387A JP S6484942 A JPS6484942 A JP S6484942A
Authority
JP
Japan
Prior art keywords
memory
bus
microprocessor
block
nok
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24218387A
Other languages
Japanese (ja)
Inventor
Kazuo Tsuzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24218387A priority Critical patent/JPS6484942A/en
Publication of JPS6484942A publication Critical patent/JPS6484942A/en
Pending legal-status Critical Current

Links

Landscapes

  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To prevent the lowering of the processing ability of a microprocessor bus by providing a three port memory and a bus exclusive-use for transferring data separately from a processor bus. CONSTITUTION:A packet received from a line 11 is stored into one of memory blocks 101-10k of a three-ports memory 13 by a data transfer control circuit 12 (it is tentatively stored into the 101). Next, a microprocessor 1 writes, to a memory buffer selecting register 110 for a second port, a high order memory address value corresponding to the block 101, writes the high order address value (for example nok) of the memory block to be transferred to a selecting register n10, and activates a control circuit 3. Then, the packet is transferred from the block 110 through a data transferring bus 5 to the nok. In such a way, the lowering of the processing ability of the microprocessor can be prevented.
JP24218387A 1987-09-25 1987-09-25 Packet buffer control system Pending JPS6484942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24218387A JPS6484942A (en) 1987-09-25 1987-09-25 Packet buffer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24218387A JPS6484942A (en) 1987-09-25 1987-09-25 Packet buffer control system

Publications (1)

Publication Number Publication Date
JPS6484942A true JPS6484942A (en) 1989-03-30

Family

ID=17085541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24218387A Pending JPS6484942A (en) 1987-09-25 1987-09-25 Packet buffer control system

Country Status (1)

Country Link
JP (1) JPS6484942A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60110067A (en) * 1983-11-21 1985-06-15 Mitsubishi Electric Corp Simple memory data transfer device
JPS61217858A (en) * 1985-03-25 1986-09-27 Hitachi Ltd Data transmitting device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60110067A (en) * 1983-11-21 1985-06-15 Mitsubishi Electric Corp Simple memory data transfer device
JPS61217858A (en) * 1985-03-25 1986-09-27 Hitachi Ltd Data transmitting device

Similar Documents

Publication Publication Date Title
JPS57105879A (en) Control system for storage device
CA2065894A1 (en) Data transfer system
JPS6484942A (en) Packet buffer control system
GB2013006A (en) Data processing system using a high speed data channel
EP0256134A4 (en) Central processing unit.
JPS57141768A (en) High speed transferring device for video information
JPS5533214A (en) Information processing system
JPS6448124A (en) Data transfer device
JPS6473458A (en) System for controlling access of vector data
JPS5487148A (en) Data processing system by multiplex processor
JPS56118132A (en) Dma data transferring system
JPS56118133A (en) Direct memory access circuit
JPS56157518A (en) Communication device between processing devices
JPS5533282A (en) Buffer control system
JPS6410377A (en) Inter-module communication system
JPS6414656A (en) Data transfer system
JPS57206949A (en) Data processing device
JPS57130165A (en) Picture processing system
JPS5759233A (en) Signal transmitting circuit
JPS57174753A (en) Information processor
JPS5622157A (en) Process system multiplexing system
JPS55135925A (en) Information transfer device
JPS5668832A (en) Data buffer control system
JPS61120262A (en) Inter-memory intelligent dma controller
JPS57192154A (en) Continuous transmitting and receiving system for block signal