JPS6486732A - Psk modulation circuit - Google Patents

Psk modulation circuit

Info

Publication number
JPS6486732A
JPS6486732A JP24485487A JP24485487A JPS6486732A JP S6486732 A JPS6486732 A JP S6486732A JP 24485487 A JP24485487 A JP 24485487A JP 24485487 A JP24485487 A JP 24485487A JP S6486732 A JPS6486732 A JP S6486732A
Authority
JP
Japan
Prior art keywords
rom
signal
carrier
psk
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24485487A
Other languages
Japanese (ja)
Inventor
Shigeyuki Furushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP24485487A priority Critical patent/JPS6486732A/en
Publication of JPS6486732A publication Critical patent/JPS6486732A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To accurately keep the phase difference between 0 deg. and 180 deg. carrier signals at 180 deg. by storing 0 deg. and 180 deg. carrier signals of a PSK modulated signal in two ROMs and switching outputs of ROMs by a PCM input signal and converting the output to an analog signal by a D/A converting circuit. CONSTITUTION:A clock signal 1 for PSK carrier has the frequency divided by M in a counter 2 to become an address signal 3 of a ROM 4 and a ROM 5. One-cycle components of sine waves for carrier are stored in the ROM 4, and one-cycle components of sine waves 180 deg. phase-delayed behind sine waves stored in the ROM 4 are stored in the same address as the ROM 4 in the ROM 5. The ROM 4 is selected when a PCM input signal 6 is in a high level, and the ROM 5 is selected when the signal 6 is in a low level. Therefore, the 0 deg. carrier data signal is outputted when the PCM input signal 6 is in the high level, and the 180 deg. carrier data signal is outputed when it is in the low level. An N-bit data signal 8 of the ROM output is converted to a PSK output signal 11 by a D/A converting circuit 9.
JP24485487A 1987-09-29 1987-09-29 Psk modulation circuit Pending JPS6486732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24485487A JPS6486732A (en) 1987-09-29 1987-09-29 Psk modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24485487A JPS6486732A (en) 1987-09-29 1987-09-29 Psk modulation circuit

Publications (1)

Publication Number Publication Date
JPS6486732A true JPS6486732A (en) 1989-03-31

Family

ID=17124970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24485487A Pending JPS6486732A (en) 1987-09-29 1987-09-29 Psk modulation circuit

Country Status (1)

Country Link
JP (1) JPS6486732A (en)

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