JPS648757U - - Google Patents

Info

Publication number
JPS648757U
JPS648757U JP1987103430U JP10343087U JPS648757U JP S648757 U JPS648757 U JP S648757U JP 1987103430 U JP1987103430 U JP 1987103430U JP 10343087 U JP10343087 U JP 10343087U JP S648757 U JPS648757 U JP S648757U
Authority
JP
Japan
Prior art keywords
light emitting
semiconductor light
emitting element
transistor
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987103430U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987103430U priority Critical patent/JPS648757U/ja
Publication of JPS648757U publication Critical patent/JPS648757U/ja
Pending legal-status Critical Current

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  • Optical Communication System (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例の回路構成を示す
図、第2図は第1図に示した回路構成の各部の信
号波形を示す図、第3図は従来の光送信器の回路
構成を示す図、第4図は第3図に示した回路構成
の各部の信号波形を示す図である。 図において、1は信号入力端子、2はFET、
3はバイアス抵抗、4はバイアス用電源端子、5
はFETのソース端子、6は半導体発光素子、7
は抵抗、8はコンデンサ、9は同軸短絡反射線路
、10は信号入力端子、11は半導体発光素子駆
動回路、12は半導体発光素子、13はトランジ
スタ、14は抵抗、15はコンデンサである。な
お、図中、同一あるいは相当部分には同一符号を
付して示してある。
Fig. 1 is a diagram showing the circuit configuration of an embodiment of this invention, Fig. 2 is a diagram showing signal waveforms of each part of the circuit configuration shown in Fig. 1, and Fig. 3 is the circuit configuration of a conventional optical transmitter. FIG. 4 is a diagram showing signal waveforms at various parts of the circuit configuration shown in FIG. 3. In the figure, 1 is a signal input terminal, 2 is a FET,
3 is a bias resistor, 4 is a bias power supply terminal, 5
is the source terminal of the FET, 6 is the semiconductor light emitting device, and 7 is the source terminal of the FET.
8 is a resistor, 8 is a capacitor, 9 is a coaxial short-circuited reflection line, 10 is a signal input terminal, 11 is a semiconductor light emitting device drive circuit, 12 is a semiconductor light emitting device, 13 is a transistor, 14 is a resistor, and 15 is a capacitor. In the drawings, the same or corresponding parts are designated by the same reference numerals.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体発光素子と、上記半導体発光素子を駆動
する半導体発光素子駆動回路と、上記半導体発光
素子と並列接続したトランジスタと、上記トラン
ジスタのコレクタ・ベース間に接続した抵抗と、
上記トランジスタのベース・エミツタ間に接続し
たコンデンサとを備えた光送信器。
a semiconductor light emitting element, a semiconductor light emitting element driving circuit for driving the semiconductor light emitting element, a transistor connected in parallel with the semiconductor light emitting element, and a resistor connected between the collector and base of the transistor;
An optical transmitter comprising a capacitor connected between the base and emitter of the above transistor.
JP1987103430U 1987-07-06 1987-07-06 Pending JPS648757U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987103430U JPS648757U (en) 1987-07-06 1987-07-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987103430U JPS648757U (en) 1987-07-06 1987-07-06

Publications (1)

Publication Number Publication Date
JPS648757U true JPS648757U (en) 1989-01-18

Family

ID=31334255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987103430U Pending JPS648757U (en) 1987-07-06 1987-07-06

Country Status (1)

Country Link
JP (1) JPS648757U (en)

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