JPS6489441A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6489441A
JPS6489441A JP62246003A JP24600387A JPS6489441A JP S6489441 A JPS6489441 A JP S6489441A JP 62246003 A JP62246003 A JP 62246003A JP 24600387 A JP24600387 A JP 24600387A JP S6489441 A JPS6489441 A JP S6489441A
Authority
JP
Japan
Prior art keywords
wiring
integrated circuit
high speed
circuit chip
base board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62246003A
Other languages
Japanese (ja)
Inventor
Tomoaki Takubo
Toshio Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62246003A priority Critical patent/JPS6489441A/en
Publication of JPS6489441A publication Critical patent/JPS6489441A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To display the high speed performance of a chip sufficiently, by constituting a feed-through wiring on a package with a wiring pattern without change in characteristic impedance due to bending. CONSTITUTION:A first wiring 4 is arranged from the side of a base board 1, where an outer lead 3 is provided, to the opposite side in a straight line shape without bending in halfway through a part underneath an integrated circuit chip 2. The wiring is terminated at the opposite side. The first wiring 4 is connected to the integrated circuit chip 2 by way of a through hole wiring 6, which is a second wiring. The wiring 6 is branched in the direction of the thickness of the base board 1 and arranged to an electrode 5 of on the surface of the base board 1. The electrode 5 and a pad on the integrated circuit chip 2 are connected with a bonding wire 7. Therefore, there is no ununiformity in characteristic impedance in the wiring of a high speed signal input part. As a result, the high speed input signal is supplied to the integrated circuit chip without waveform distortion. Thus the high speed property of the chip is utilized.
JP62246003A 1987-09-30 1987-09-30 Semiconductor integrated circuit device Pending JPS6489441A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62246003A JPS6489441A (en) 1987-09-30 1987-09-30 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62246003A JPS6489441A (en) 1987-09-30 1987-09-30 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6489441A true JPS6489441A (en) 1989-04-03

Family

ID=17142019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246003A Pending JPS6489441A (en) 1987-09-30 1987-09-30 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6489441A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002232060A (en) * 2001-02-01 2002-08-16 Mitsubishi Electric Corp Substrate with power supply line, optical semiconductor device using the same, and method of supplying power to optical semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002232060A (en) * 2001-02-01 2002-08-16 Mitsubishi Electric Corp Substrate with power supply line, optical semiconductor device using the same, and method of supplying power to optical semiconductor element

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