JPS649548A - Cache memory device - Google Patents

Cache memory device

Info

Publication number
JPS649548A
JPS649548A JP62165665A JP16566587A JPS649548A JP S649548 A JPS649548 A JP S649548A JP 62165665 A JP62165665 A JP 62165665A JP 16566587 A JP16566587 A JP 16566587A JP S649548 A JPS649548 A JP S649548A
Authority
JP
Japan
Prior art keywords
cache
memory access
bank
host
avoid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62165665A
Other languages
Japanese (ja)
Inventor
Yasushi Oi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62165665A priority Critical patent/JPS649548A/en
Publication of JPS649548A publication Critical patent/JPS649548A/en
Pending legal-status Critical Current

Links

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To avoid contention of an address memory access and data memory access by decoding an address signal outputted from a host and outputting a bank select signal to a cache bank and a pre-fetch request signal to other cache banks than the former bank at the same time. CONSTITUTION:The arrangement of cache blocks are interleaved to plural independent cache banks 102-105 to separate the cache access from a host 101 side and cache fetch from system buses 153-155 between banks completely to avoid the data memory access. Furthermore, the pre-fetch lookup control is executed by the cache control bank different from that accessed by the host 101 to avoid the contention of the address memory access.
JP62165665A 1987-07-01 1987-07-01 Cache memory device Pending JPS649548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62165665A JPS649548A (en) 1987-07-01 1987-07-01 Cache memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62165665A JPS649548A (en) 1987-07-01 1987-07-01 Cache memory device

Publications (1)

Publication Number Publication Date
JPS649548A true JPS649548A (en) 1989-01-12

Family

ID=15816687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62165665A Pending JPS649548A (en) 1987-07-01 1987-07-01 Cache memory device

Country Status (1)

Country Link
JP (1) JPS649548A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003007155A1 (en) * 2001-07-12 2003-01-23 Ip Flex Inc. Integrated circuit device
JP2006012133A (en) * 2004-05-28 2006-01-12 Intel Corp Multiprocessor chip with bi-directional ring interconnect
JP2007189910A (en) * 2006-01-17 2007-08-02 Shimizu Corp Greening unit and greening system including the greening unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003007155A1 (en) * 2001-07-12 2003-01-23 Ip Flex Inc. Integrated circuit device
US6868017B2 (en) 2001-07-12 2005-03-15 Ip Flex Inc. Integrated circuit device
JP2006012133A (en) * 2004-05-28 2006-01-12 Intel Corp Multiprocessor chip with bi-directional ring interconnect
JP2007189910A (en) * 2006-01-17 2007-08-02 Shimizu Corp Greening unit and greening system including the greening unit

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