KR20050009779A - Liquid crystal display and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device, comprising: a liquid crystal panel assembly including a plurality of pixels arranged in a matrix, a latch for storing image data, the data voltage corresponding to the image data; A data driver applied to a pixel and comparing pixel data of a pixel unit of the image data with pixel data of a previous row to transmit a corresponding information signal to the data driver, and transmitting the pixel data to the data driver, wherein the pixel data And a signal controller not transmitting the pixel data to the data driver if the pixel data of the previous row is the same. According to the present invention can minimize the data transmission to reduce power consumption and EMI due to the data transmission.

Description

Liquid crystal display and driving method thereof {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

The present invention relates to a liquid crystal display and a driving method thereof.

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal display devices are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

Image data for driving such a TFT-LCD is transmitted to a signal controller of a liquid crystal display in a form of a complementary metal oxide semiconductor (CMOS) signal or a low voltage differential signal (LVDS) from a computer or a graphic controller in most cases. After data restoration or image processing, it is converted into CMOS data and transmitted to the data driver of the TFT-LCD. The image data transmitted in units of rows is converted into an analog gray voltage in a data driving IC (attached circuit) attached to the liquid crystal panel to drive the display panel. In general, a row of data is stored in the data driving IC to display the display panel at the same time. Drive. Therefore, while the data of one row is always sampled, the data of the previous row is stored in the data driver IC.

Except for moving picture screens, in which image data is constantly changing spatially and temporally, a screen displayed on a liquid crystal display generally has a very simple display pattern, and a large part of the screen has the same color and same brightness. However, the screen of the liquid crystal display is not changed or the image data is always transmitted. This new data change every row causes a waste of power. In particular, including the case of a liquid crystal display device for a notebook PC, it is essential to drive the liquid crystal display device at low power, and efforts are being actively made to lower power consumption in various ways.

Accordingly, an object of the present invention is to provide a liquid crystal display device which can reduce power consumption and reduce EMI by minimizing data transmission.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a data driver of a liquid crystal display according to an exemplary embodiment of the present invention.

4 shows a display pattern in a liquid crystal display and a data transmission control signal according to an embodiment of the present invention.

According to an exemplary embodiment of the present invention, a liquid crystal display includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines and arranged in a matrix. A liquid crystal panel assembly comprising: a liquid crystal panel assembly; a latch for storing image data; a data driver for applying a data voltage corresponding to the image data to the pixel; and comparing pixel data of a pixel unit of the image data with pixel data of a previous row. And a signal controller which transmits a corresponding information signal to the data driver and transmits the pixel data to the data driver, but does not transmit the pixel data to the data driver when the pixel data and the pixel data of the previous row are the same. . In this case, the data driver includes a data selector for selectively providing the pixel data to the latch according to the information signal.

The data driver further includes a shift register for shifting the pixel data to store the pixel data in the latch, wherein the data selector is comprised of a plurality of AND products, and the AND product is a shift of the shift register. Preferably, a clock and the information signal are received and output to the latch.

When the data driver does not receive the pixel data, it is preferable to apply a data voltage corresponding to the stored data to the pixel again.

The information signal is low level if the pixel data is the same as the pixel data of the previous row, and high level if it is different.

The signal controller may include a row memory for comparing the pixel data.

In addition, the driving method of the liquid crystal display device according to another embodiment of the present invention is a driving method of a liquid crystal display device including a plurality of pixels arranged in the form of a matrix, the method comprising: storing the row data, the row data in pixel units And comparing the row data of the previous row with the row data of the previous row, and transmitting and receiving the pixel data if the pixel data is different from the pixel data of the previous row, and not transmitting and receiving the pixel data.

The method may further include applying the pixel data to the corresponding pixel when transmitting and receiving the pixel data, and applying the pixel data of the previous row to the corresponding pixel again when the pixel data is not transmitted or received.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display and a driving method thereof according to an embodiment of the present invention will now be described in detail with reference to the drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by superimposing a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n and usually consists of a plurality of gate driving ICs 440.

The data driver 500 is connected to the data lines D ₁ -Dm of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. IC 540.

A plurality of gate drive integrated circuits or data drive integrated circuits may be mounted in a tape carrier package (TCP) (not shown) to attach TCP to the liquid crystal panel assembly 300, or to integrate these onto a glass substrate without using TCP. Circuits may be directly attached (chip on glass, COG mounting method), and circuits performing the same functions as those integrated circuits may be directly mounted on the liquid crystal panel assembly 300.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 properly processes the image signals R, G, and B according to the operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate control signal. After generating the CONT1 and the data control signal CONT2 and the like, the gate control signal CONT1 is sent to the gate driver 400 and the data control signal CONT2 and the processed image signals R ', G', and B 'are processed. ) Is sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal), a gate clock signal CPV for controlling the output timing of the gate-on pulse, and a gate-on pulse. And an output enable signal OE that defines the width of the signal.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the 800.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that one row of switching elements Q connected thereto is turned on (this period is referred to as "1H" or "1 horizontal period ( horizontal period) "and the same as one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV], and the data driver 500 converts each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) within one frame or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS ( "Dot reversal").

3 and 4, a liquid crystal display device capable of minimizing data transmission will be described in detail.

3 is a block diagram of a data driver 500 of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a display pattern of the liquid crystal display and a data transmission control signal according to an embodiment of the present invention. DTC).

The signal controller 600 has a row memory (not shown) capable of storing image data (hereinafter referred to as "row data") for one pixel row, and stores the input row data in this row memory. When arbitrary row data is input, the signal controller 600 reads out the row data of the previous row stored in the memory and compares the row data of the pixel data in units of image data (hereinafter referred to as "pixel data") for each pixel. It generates a data transmission control signal (DTC) indicating whether the same. Thereafter, the signal controller 600 transmits the data transmission control signal DTC to the data driver 500. In this case, the signal controller 600 selectively transmits the pixel data to the data driver 500 according to whether the pixel data are the same.

In the example shown in Figs. 3 and 4, when certain pixel data is the same as the pixel data of the previous row, the data transmission control signal DTC is set to the low ("L") level, and otherwise is set to the high ("H") level. The signal controller 600 transmits the corresponding pixel data when the data transmission control signal DTC is high level, and does not transmit the corresponding pixel data when the data transmission control signal DTC is low.

The data driver 500 of the liquid crystal display according to the exemplary embodiment of FIG. 3 may include a reduced swing differential signaling (RSDS) receiver 45, a data register 46, a shift register 40, and a first latch. 41, a second latch 42, a digital-to-analog converter 43, an output buffer 44, and a plurality of AND gates 47.

The RSDS receiver 45 receives an RSDS signal transmitted from the signal controller 600 and converts the RSDS signal into TTL / CMOS data. The shift register 40 sequentially shifts the converted data through the data register 46 by the shift clock and stores the shifted data in the first latch 41. When all the row data of the first latch 41 is stored in the first latch 41, the data stored by the load signal LOAD from the signal controller 600 is again stored in the second latch 42. Data stored in the second latch 42 is converted into an analog data voltage through the digital-to-analog converter 43 and applied to the data lines D ₁ -D _m through the output buffer 44.

Although the first latch 41 sends a plurality of stored pixel data to the second latch 42 by the load signal LOAD, the first latch 41 continues the pixel data until the next corresponding shift clock is turned on from the shift register 40. Save it.

On the other hand, the plurality of AND products 47 are located between the shift register 40 and the first latch 41. Each logical AND element 47 corresponding to each pixel receives the corresponding shift clock of the shift register 40 and the data transfer control signal DTC from the signal controller 600, and outputs an output signal to the first latch 41. Input the corresponding data enable terminal of

Accordingly, the first latch 41 receives the corresponding pixel data from the signal controller 600 only when the shift clock and the data transmission control signal DTC become high levels for each pixel. Even when the shift clock is at the high level, when the data transfer control signal DTC is at the low level, that is, when the pixel data of the current row is the same as the pixel data of the previous row, the first latch 41 does not receive the pixel data. In this case, the pixel data of the previous row stored in the first latch 41 is transferred to the second latch 42 by the load signal LOAD.

As shown in the upper part of FIG. 4, the display pattern in the liquid crystal display which consists of 8 * 9 pixels is demonstrated as an example. 4 illustrates a data transmission control signal DTC generated by the signal controller 600 according to the upper display pattern.

When displaying the “H” pattern as shown in FIG. 4, the signal controller 600 sequentially transmits the entire first row data to the data driver 500. At the same time, the data transmission control signal DTC is all set to a high level for each pixel and transmitted to the data driver 500. As a result, the output of each AND device 47 of the data driver 500 is at a high level, and the first latch 41 receives all of the first row data. Thereafter, the first row data stored in the first latch 41 is transferred to the second latch 42 according to the load signal.

In the case of the second row data, the signal controller 600 compares the second row data with the first row data. As a result of the comparison, the signal controller 600 does not transmit the same first, fourth, fifth, and eighth pixel data of the previous row to the data driver 500, and low-level the data transfer control signal DTC for each corresponding pixel. To the data driver 500. The signal controller 600 transmits the second, third, sixth, and seventh column pixel data different from the previous row to the data driver 500, and transmits the data transmission control signal DTC for each corresponding pixel at a high level. . Then, the AND product 47 of the data driver 500 selectively operates the first latch 41 according to the data transmission control signal DTC. That is, when the data transfer control signal DTC is at the low level, the first latch 41 does not receive the pixel data and continuously stores the pixel data of the previous row. In contrast, when the data transmission control signal DTC is at a high level, the first latch 41 receives pixel data and stores new pixel data. The pixel data stored in the first latch 41 is transferred to the second latch 42 according to the load signal LOAD.

The signal controller 600 then compares the third row data with the second row data. As a result of the comparison, since the pixel data of all columns is the same, the signal controller 600 transmits all of the data transmission control signals DTC to the low level without transmitting pixel data to the data driver 500. As a result, the output of the AND product 47 of the data driver 500 is at a low level. Accordingly, the first latch 41 is disabled and the second row of pixel data stored in the first latch 41 is loaded. It is transmitted to the second latch 42 again in accordance with the signal LOAD.

The signal controller 600 and the data driver 500 repeat the above operation with respect to the remaining rows to transmit data up to the ninth row to the first latch 41 and display the data on the LCD screen.

As a result, the pixel data transmitted from the signal controller 600 to the data driver 500 to display one frame is 20 pixel data among the 72 pixel data, and the data rate is approximately 28%. As such, the pixel data is transmitted only when the data transfer control signal DTC is at the high level because the pixel data is the same as the pixel data of the previous row, and thus the data rate is significantly reduced.

In conclusion, when the pixel data is identical to the pixel data of the previous row, the present invention stores the signal controller 600 in the first latch 41 of the data driver 500 without transmitting the pixel data to the data driver 500. If the pixel data of the previous row is used as it is, the operation associated with data transmission and reception is not performed, thereby reducing power consumption and EMI.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As such, when any pixel data displayed on the liquid crystal display is the same as the pixel data of the previous row, the signal controller does not transmit the pixel data to the data driver but uses the pixel data of the previous row stored in the latch of the data driver as it is. By doing so, it does not perform the operations associated with data transmission and reception, thereby reducing power consumption and reducing EMI.

Claims (7)

A liquid crystal panel assembly comprising a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines, respectively, and arranged in a matrix form; A data driver which includes a latch for storing image data, and applies a data voltage corresponding to the image data to the pixel; Compare the pixel data of the pixel unit of the image data with the pixel data of the previous row and transmit the corresponding information signal to the data driver, and transmit the pixel data to the data driver, but the pixel data and the pixel data of the previous row. Is a signal controller that does not transmit the pixel data to the data driver. Including; The data driver includes a data selector for selectively providing the pixel data to the latch according to the information signal. Liquid crystal display. In claim 1, The data driver further includes a shift register for shifting the pixel data to store the pixel data in the latch, The data selector is composed of a plurality of AND products. The AND device receives the shift clock and the information signal of the shift register and outputs the information to the latch. Liquid crystal display. In claim 2, And when the data driver does not receive the pixel data, applies the data voltage corresponding to the stored data to the pixel again. The method of claim 2 or 3, And the information signal is low level if the pixel data is the same as the pixel data of the previous row, and is high level otherwise. The method according to any one of claims 1 to 3, And the signal controller includes a row memory for comparing the pixel data. A driving method of a liquid crystal display device including a plurality of pixels arranged in a matrix form, Storing row data, Comparing the row data with the row data of the previous row on a pixel basis; and Transmitting and receiving the pixel data if the pixel data is different from the pixel data of the previous row, and not transmitting and receiving the pixel data. Method of driving a liquid crystal display comprising a. In claim 6, And applying the pixel data to the corresponding pixel when the pixel data is transmitted and received, and applying the pixel data of the previous row to the corresponding pixel again when the pixel data is not transmitted or received.