KR20070093046A - 반도체 제조를 위한 탄력적 혼성 결함 분류 - Google Patents
반도체 제조를 위한 탄력적 혼성 결함 분류 Download PDFInfo
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- KR20070093046A KR20070093046A KR1020077009123A KR20077009123A KR20070093046A KR 20070093046 A KR20070093046 A KR 20070093046A KR 1020077009123 A KR1020077009123 A KR 1020077009123A KR 20077009123 A KR20077009123 A KR 20077009123A KR 20070093046 A KR20070093046 A KR 20070093046A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B5/00—Measuring arrangements characterised by the use of mechanical techniques
- G01B5/28—Measuring arrangements characterised by the use of mechanical techniques for measuring roughness or irregularity of surfaces
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/08—Locating faults in cables, transmission lines, or networks
- G01R31/10—Locating faults in cables, transmission lines, or networks by increasing destruction at fault, e.g. burning-in by using a pulse generator operating a special program
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2846—Fault-finding or characterising using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/24—Indexing scheme for image data processing or generation, in general involving graphical user interfaces [GUIs]
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30148—Semiconductor; IC; Wafer
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- Quality & Reliability (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Theoretical Computer Science (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Abstract
Description
Claims (20)
- 결함에 대한 규칙의 시퀀스를 반도체 표본의 검사에 의해서 생성된 검사 데이터에 적용하는 단계; 및상기 적용하는 단계의 결과에 기초하여 상기 결함을 분류하는 단계를 포함하고,상기 규칙의 시퀀스는 통계 규칙(statistic rule), 확정 규칙(deterministic rule), 통계와 확정의 혼성 규칙, 또는 이들의 일부 조합을 포함하는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 확정 규칙은 하나 이상의 테스트를 상기 결함의 특성에 적용시키고, 상기 특성은 상기 결함이 밝은지 또는 어두운지 여부, 백그라운드에 대한 결함의 콘트라스트, 측정된 사이즈, 검출 방법, 표본의 다른 레벨의 결함에 관한 정보, 표본의 결함의 위치, 다른 이벤트와의 근접성, 또는 결함을 확정 방식을 분류하는데 사용될 수 있는 속성의 일부 조합을 포함하는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 통계 규칙은 색상, 사이즈, 선예도, 이심율, 진원도, 투명성, 텍스처, 콘텍스트, 또는 이들의 일부 조합을 포함하는 결함의 특성에 기초하는 것이고, 상기 통계 규칙은 결함을 빈에 통계 방식으로 넣도록 특성을 적용하 는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 적용하는 단계에 이용되는 상기 통계 규칙과 상기 확정 규칙에 대한 결함 입력의 특성은 사용자에 의해 선택되는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 규칙의 시퀀스의 일부는 상기 결함이 검사 도중에 발견될 때 적용되고, 상기규칙의 시퀀스의 다른 일부는 상기 검사의 종료시에 적용되며, 상기 규칙의 시퀀스의 상기 다른 일부는 표본에서의 다른 결함과 상기 결함간의 근접성 또는 이전 표본의 이력에 기초한 규칙을 포함하고, 상기 다른 일부가 적용된 후에 종속 규칙이 적용되는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 적용하는 단계는 사용자가 상기 결함을 관찰하는 동안 수행되는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 분류의 결과에 기초하여 검사 레시피를 조정하는 단계를 더 포함하는, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 후속 작용을 위해서 결함을 샘플링함에 있어서 상기 분류의 결과를 이용하는 단계를 더 포함하는, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 분류의 결과를 이용하여 엔지니어링 분석을 행하는 단계를 더 포함하는, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상이한 하드웨어 구성을 갖는 상이한 검사 또는 관찰 툴에 의해 생성된 데이터에 상기 컴퓨터 구현 방법을 수행시키는 단계를 더 포함하는, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 분류의 결과는 상기 결함에 대한 다수의 출력 분류를 포함하는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 분류하는 단계는 상기 결함이 상기 확정 규칙 또는, 상기 확정 규칙과 통계 규칙의 조합을 적용한 결과에 기초한 뉘상스(nuisance) 결함인지를 판정하는 단계를 포함하는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 통계 규칙 및 상기 통계와 확정의 혼성 규칙은 사용자가 이 규칙들을 이해하는 것을 돕고 그리고 상기 사용자의 의도를 반영하는 분류를 제공하도록 선택하기 위해 그룹으로 편성되는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 통계 규칙은 개별적으로 가중부여되는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제1항에 있어서, 상기 규칙의 시퀀스는 사용자가 쌍방향 사용자 인터페이스를 이용해 작업하여 편성되고, 상기 규칙의 시퀀스는 상이한 레벨을 갖는 트리로서 상기 쌍방향 사용자 인터페이스에 표현되는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제15항에 있어서, 상기 트리는 하나 이상의 브랜치, 하나 이상의 종단 빈, 또는 이들의 일부 조합을 생성하는 노드를 포함하는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제15항에 있어서, 상기 트리는 확정 노드, 통계 노드, 또는 확정과 통계의 혼성 노드를 포함하는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제15항에 있어서, 상기 트리는 특성 이름에 의해 지정되는 확정 노드, 이름에 의해 지정되는 통계 노드, 이름에 의해 지정되는 혼성 노드를 포함하는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 상기 쌍방향 사용자 인터페이스는 그래픽으로 그리고 샘플 이미지와 함께 상기 분류의 결과를 나타내는 것인, 결함을 분류하기 위한 탄력적 컴퓨터 구현 방법.
- 제15항에 있어서, 상기 쌍방향 사용자 인터페이스를 이용하여 제한이 없는 불 연산자를 결함 특성에 적용하는 것을 통해서 상기 확정 규칙 중 하나를 세우는 단계를 더 포함하는, 결함을 분류하는 방법을 위한 탄력적 컴퓨터 구현 방법.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/954,968 US7142992B1 (en) | 2004-09-30 | 2004-09-30 | Flexible hybrid defect classification for semiconductor manufacturing |
| US10/954,968 | 2004-09-30 | ||
| PCT/US2005/035357 WO2006039584A1 (en) | 2004-09-30 | 2005-09-30 | Flexible hybrid defect classification for semiconductor manufacturing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20070093046A true KR20070093046A (ko) | 2007-09-17 |
| KR101144545B1 KR101144545B1 (ko) | 2012-05-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020077009123A Expired - Fee Related KR101144545B1 (ko) | 2004-09-30 | 2005-09-30 | 반도체 제조를 위한 탄력적 혼성 결함 분류 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7142992B1 (ko) |
| JP (1) | JP5102035B2 (ko) |
| KR (1) | KR101144545B1 (ko) |
| WO (1) | WO2006039584A1 (ko) |
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| WO2016002003A1 (ja) * | 2014-07-01 | 2016-01-07 | 株式会社日立ハイテクノロジーズ | 基板検査装置及び方法 |
| US9582869B2 (en) * | 2014-10-19 | 2017-02-28 | Kla-Tencor Corp. | Dynamic binning for diversification and defect discovery |
| JP7015235B2 (ja) * | 2015-08-05 | 2022-02-02 | ケーエルエー コーポレイション | 範囲に基づくリアルタイム走査電子顕微鏡非可視ビナー |
| KR101670235B1 (ko) | 2015-08-12 | 2016-11-09 | 한국수력원자력 주식회사 | 원전의 결함 정보 분석 시스템 및 방법 |
| KR102724160B1 (ko) * | 2016-11-29 | 2024-11-01 | 삼성전자주식회사 | 웨이퍼를 검사하기 위한 검사 장치 및 이를 이용한 웨이퍼의 검사 방법 |
| US11047806B2 (en) * | 2016-11-30 | 2021-06-29 | Kla-Tencor Corporation | Defect discovery and recipe optimization for inspection of three-dimensional semiconductor structures |
| US11237119B2 (en) * | 2017-01-10 | 2022-02-01 | Kla-Tencor Corporation | Diagnostic methods for the classifiers and the defects captured by optical tools |
| CN110874839A (zh) * | 2019-11-19 | 2020-03-10 | 上海华力微电子有限公司 | 晶圆图形提取方法及其提取系统 |
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| US5923430A (en) * | 1993-06-17 | 1999-07-13 | Ultrapointe Corporation | Method for characterizing defects on semiconductor wafers |
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| US5822218A (en) * | 1996-08-27 | 1998-10-13 | Clemson University | Systems, methods and computer program products for prediction of defect-related failures in integrated circuits |
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| JP2001274209A (ja) * | 2000-03-28 | 2001-10-05 | Toshiba Corp | 半導体検査装置、半導体欠陥解析装置、半導体設計データ修正装置、半導体検査方法、半導体欠陥解析方法、半導体設計データ修正方法およびコンピュータ読み取り可能な記録媒体 |
| JP2002162366A (ja) * | 2000-11-27 | 2002-06-07 | Hitachi Ltd | 欠陥検査方法とその装置、及び欠陥の自動分類のための欠陥位置検出方法 |
| JP2002228606A (ja) * | 2001-01-31 | 2002-08-14 | Hitachi Ltd | 電子線式回路パターンの検査方法および装置 |
| JP4118703B2 (ja) * | 2002-05-23 | 2008-07-16 | 株式会社日立ハイテクノロジーズ | 欠陥分類装置及び欠陥自動分類方法並びに欠陥検査方法及び処理装置 |
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2004
- 2004-09-30 US US10/954,968 patent/US7142992B1/en not_active Expired - Lifetime
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2005
- 2005-09-30 KR KR1020077009123A patent/KR101144545B1/ko not_active Expired - Fee Related
- 2005-09-30 WO PCT/US2005/035357 patent/WO2006039584A1/en not_active Ceased
- 2005-09-30 JP JP2007534830A patent/JP5102035B2/ja not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| WO2006039584A1 (en) | 2006-04-13 |
| US20060265145A1 (en) | 2006-11-23 |
| JP2008515239A (ja) | 2008-05-08 |
| KR101144545B1 (ko) | 2012-05-11 |
| JP5102035B2 (ja) | 2012-12-19 |
| US7142992B1 (en) | 2006-11-28 |
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