KR20090105977A - 저유전율막의 개질제 및 제조방법 - Google Patents

저유전율막의 개질제 및 제조방법 Download PDF

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KR20090105977A
KR20090105977A KR1020097018100A KR20097018100A KR20090105977A KR 20090105977 A KR20090105977 A KR 20090105977A KR 1020097018100 A KR1020097018100 A KR 1020097018100A KR 20097018100 A KR20097018100 A KR 20097018100A KR 20090105977 A KR20090105977 A KR 20090105977A
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dielectric constant
low dielectric
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constant film
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쯔요시 오가와
미쯔야 오하시
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샌트랄 글래스 컴퍼니 리미티드
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane

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Abstract

본 발명의 저유전율막의 개질제는, 반도체 디바이스에 사용되는 저유전율막의 비유전율을 저하시키기 위한 개질제로서, 식(1)
Figure 112009053248476-PCT00005
(R은 C1~C4의 알킬기, n은 0~3의 정수)로 표시되는 규소 화합물을 유효성분으로서 함유하는 것을 특징으로 한다.

Description

저유전율막의 개질제 및 제조방법{Modifier for low dielectric constant film, and method for production thereof}
본 발명은 반도체 디바이스에 사용되는 저유전율막에 있어서, 저유전율막의 비유전율을 저하시키기 위해 사용되는 저유전율막의 개질제 및 개질된 저유전율막의 제조방법에 관한 것이다.
최근의 고집적화된 반도체에 있어서는, 디바이스 내의 신호 지연 문제를 해소하여, 보다 고속이며 전력절약의 디바이스를 제조하기 위해, 층간 절연막으로서 저유전율막이 사용되고 있다. 저유전율막에는, 유기계, 무기계를 포함하여, 수많은 종류가 있지만, 현재, 가장 일반적인 것은, 실리카막에 탄소를 첨가한 SiOC막이다. 향후, 반도체 디바이스가 더욱 미세화되면, SiOC막에 있어서도 충분한 저유전율 특성이 얻어지지 않는 점에서, 층간 절연막에는 다공질화된 SiOC막이 사용될 전망이다.
그러나 SiOC막은 성막 후부터 막 중의 Si-C 결합이나 Si-H 결합이 절단되어, 실란올(Si-OH)이 발생하고, 막의 비유전율이 상승한다는 문제가 있다. 이와 같은 문제를 해소하기 위해, SiOC막에 HMDS(헥사메틸디실라잔)와 같은 실란커플링제를 막의 개질제로서 작용시켜, 실란올을 화학적으로 실릴화하여, 막의 비유전율을 저 하시키는 방법이 공지로 되어 있다. 또한, 최근에는, HMDS 대신에, TMS-Cl(트리메틸클로로실란)이나 TMSDMA(트리메틸실릴디메틸아민) 등을 사용한 방법도 보고되어 있다(특허문헌 1). 그러나, 어느 방법에 있어서도, 얻어지는 막의 비유전율은 만족되지 않았다.
따라서, SiOC막과 같은 저유전율막에 대해, 막 중의 실란올을 가능한 한 화학적으로 실릴화하여, 만족되는 막의 비유전율까지 저하시키도록 개질할 수 있는 화합물이 요망되고 있다.
특허문헌 1: 일본국 특허공개 제2006-179913호 공보
발명의 개요
본 발명은 반도체 디바이스에 사용되는 저유전율막에 대해, 막 중의 실란올을 화학적으로 실릴화하여, 막의 비유전율이 저하되도록 개질할 수 있는 개질제를 제공하는 것을 목적으로 하고 있다.
더 나아가서는, 개질제에 의해 비유전율을 저하시킨 저유전율막의 제조방법을 제공하는 것을 목적으로 하고 있다.
본 발명자들은 상기 목적을 달성하기 위해 예의 검토를 거듭한 결과, 저유전율막에, 분자 내에 아지드기를 갖는 규소 화합물을 유효성분으로서 함유한 개질제와 접촉시킴으로써, 저유전율막 중의 실란올이 화학적으로 실릴화되어, 막의 비유전율이 저하되도록 개질할 수 있는 것을 발견하고, 본 발명에 도달한 것이다.
즉, 본 발명은 반도체 디바이스에 사용되는 저유전율막의 비유전율을 저하시키기 위한 개질제로서, 식(1)
Figure 112009053248476-PCT00001
(R은 C1~C4의 알킬기, n은 0~3의 정수)로 표시되는 규소 화합물을 유효성분으로서 함유하는 것을 특징으로 하는 저유전율막의 개질제를 제공하는 것이다.
더 나아가서는, 반도체 디바이스에 사용되는 저유전율막에 대해, 상기의 식(1)로 표시되는 규소 화합물을 함유하는 개질제를 20℃~300℃의 범위 내에서 접촉시킴으로써 되는 개질된 저유전율막의 제조방법을 제공하는 것이다.
상세한 설명
본 발명에 의하면, 저유전율막 중의 실란올을 화학적으로 실릴화하여, 저유전율막의 비유전율을 저하시켜, 막을 개질시킬 수 있다. 또한 본 발명의 방법에 의하면, 비유전율이 저하된 개질된 저유전율막을 제조할 수 있다.
이하, 본 발명을 더욱 상세하게 기술한다. 본 발명에서 저유전율막의 개질제 중에 유효성분으로서 포함되는 규소 화합물은, 식(1)
Figure 112009053248476-PCT00002
(R은 C1~C4의 알킬기, n은 0~3의 정수)로 표시되는 화합물이다. 본 발명에 있어서 C1~C4의 알킬기란, 구체적으로는, 메틸기, 에틸기, n-프로필기, i-프로필기, n-부틸기, i-부틸기, s-부틸기, t-부틸기 등이다. R이 복수 존재하는 경우에는, 이들이 서로 동일한 것이어도 되고, 상이한 것이 혼재된 것이어도 된다. 그러나 최근의 저유전율막은 다공질화가 진행되고 있어, 개질제를 막 중의 공공(空孔) 내로 침투시키기 위해서도, 이들 화합물의 분자 직경은 작은 편이 바람직하고, R로서는 특히 메틸기가 바람직하다.
본 발명에 있어서 저유전율막의 비유전율 저하의 메커니즘을 상세하게 기술한다. 저유전율막 중에 실란올이 발생하면, 막의 비유전율이 상승한다. 여기서, 개질제 중에 포함되는 식(1)로 표시되는 화합물은, 식(2)에 나타내는 반응식과 같이, 실란올의 활성수소 부분에 대해, 실릴화 반응을 행한다.
Figure 112009053248476-PCT00003
(Si’는 막을 구성하는 Si와 구별하기 위한 표기로, 식(1)의 Si에 상당하는 것이다.)
그 결과, 막 중의 실란올이 감소하여, 막의 비유전율이 저하된다. 반응 후에는 아지드화 수소(HN3)가 발생하기 때문에, 이것을 계(系)외로 배출한다. 아지드화 수소는 유해하여, 적당한 제해(除害)처리를 행한 후에 폐기한다.
식(1)로 표시되는 개질제의 유효성분은, 단일성분 또는 치환기가 상이한 복수의 성분을 조합시킨 상태로 사용해도 된다. 예를 들면, 아지도트리메틸실란((CH3)3SiN3)과 아지도트리에틸실란((CH3CH2)3SiN3)을 임의의 비율로 혼합시켜, 그들을 사용해도 된다. 또한 이들을 유효성분으로 하는 개질제는, 기존의 실란커플링제와 임의의 비율로 혼합시킨 상태로 사용해도 된다. 기존의 실란커플링제로서는, HMDS(헥사메틸디실라잔), TMDS(테트라메틸디실라잔), TMSDMA(트리메틸실릴디메틸아민), DMSDMA(디메틸실릴디메틸아민), TMSDEA(트리메틸실릴디에틸아민), B[DMA]MS(비스디메틸아미노메틸실란), B[DMA]DS(비스디메틸아미노디메틸실란), TMS-Cl(트리메틸클로로실란), TMMOS(트리메틸메톡시실란) 등을 들 수 있다. 더 나아가서는 헬륨 등의 불활성 가스로 희석해서 사용해도 된다. 어느 경우에도, 개질제 중에 식(1)로 표시되는 화합물을 일정 농도 이상 함유해 둘 필요가 있고, 그 농도로서는 1 vol%~100 vol%, 바람직하게는 50 vol%~100 vol%, 더욱 바람직하게는 95 vol%~100 vol%이다.
개질제를 저유전율막에 접촉시킬 때의 온도로서는 20℃~300℃의 범위 내가 바람직하고, 특히 60℃~200℃가 바람직하다. 온도가 20℃ 미만이 되면, 개질제 중의 유효성분과 실란올의 반응속도가 매우 느려지고, 또한, 부반응으로서 실란올의 아지드화 반응도 진행되기 때문에 바람직하지 않다. 한편, 온도가 300℃를 초과하면, 개질제 중의 유효성분의 분해가 우선적으로 발생하기 때문에 바람직하지 않다.
개질제를 저유전율막에 접촉시킬 때, 개질제는 가스상, 액상 중 어느 상태로도 사용할 수 있다. 가스상으로 사용하는 경우는, 저유전율막에 대해 직접 접촉시키면 되고, 액상으로 사용하는 경우는, 저유전율막에 대해 스핀코트시키는 방법이 바람직하다. 어느 방법에 있어서도, 대기에 폭로하지 않고 실시할 필요가 있다.
개질제를 저유전율막에 접촉시킬 때의 시간으로서는 특별히 한정되지는 않는다. 그러나, 반도체 디바이스의 제조시간을 단축화시키기 위해서도 10~120초의 접촉이 바람직하다.
개질제를 저유전율막에 접촉시킨 후에는, 장치 내를 감압으로 함으로써, 미반응의 개질제 및 반응생성물을 제거할 수 있다. 이때, 장치 내를 가온하여, 제거효율을 올려서 실시해도 된다.
본 발명에 있어서의 저유전율막은, 막 중에 공공(空孔)이 존재하고 있는 것도 포함된다. 그러나, 이들 막의 형성방법에 대해서는 특별히 한정되는 것은 아니다. 막의 형성방법으로서는, 예를 들면, 플라즈마 CVD법이나 스핀온글래스법 등을 들 수 있다.
이하, 실시예에 의해 본 발명을 구체적으로 설명한다.
실시예 1
실리콘 웨이퍼 상에 MSQ(메틸실세스퀴옥산) 용액을 스핀 도포한 후, 100℃에서 30분간, 200℃에서 1시간 베이크하여, MSQ막을 형성하였다. 얻어진 MSQ막의 비유전율을 구하기 위해, 증착법으로, 막 상에 Al 전극을 형성하여, 1 MHz에 있어서의 막의 정전용량(靜電容量)을 측정하였다. 정전용량값, 막두께, 전극면적으로부터, MSQ막의 비유전율을 산출한 바, 3.6이었다. 다음으로 MSQ막을 개질하기 위해서, 밀폐 가능한 SUS제 용기를 준비하고, MSQ막을 용기 내로 옮겼다. 용기 내를 10 Pa까지 감압으로 하고, 150℃까지 가온한 후, 개질제로서 아지도트리메틸실란((CH3)3SiN3)의 증기를 10 kPa 도입하였다. 실릴화처리는 60초간 행하였다. 개질 후의 MSQ막의 비유전율을 측정한 바, 3.2였다.
실시예 2
MSQ막의 개질제를 아지도트리에틸실란((CH3CH2)3SiN3)으로 한 것 이외에는, 실시예 1과 동일한 방법으로 실시하였다. 개질 후의 MSQ막의 비유전율은 3.3이었다.
실시예 3
MSQ막의 개질제를 아지도디메틸실란((CH3)2HSiN3)으로 한 것 이외에는, 실시예 1과 동일한 방법으로 실시하였다. 개질 후의 MSQ막의 비유전율은 3.2였다.
실시예 4
개질제 도입시의 온도를 70℃로 한 것 이외에는, 실시예 1과 동일한 방법으로 실시하였다. 개질 후의 MSQ막의 비유전율은 3.3이었다.
실시예 5
MSQ막의 개질제를 아지도트리메틸실란((CH3)3SiN3)과 HMDS(헥사메틸디실라잔)의 혼합물(혼합비 1:1)로 한 것 이외에는, 실시예 1과 동일한 방법으로 실시하였다. 개질 후의 MSQ막의 비유전율은 3.3이었다.
[비교예 1]
MSQ막의 개질제를 HMDS(헥사메틸디실라잔)로 한 것 이외에는, 실시예 1과 동일한 방법으로 실시하였다. 개질 후의 MSQ막의 비유전율은 3.4였다.
[비교예 2]
개질제 도입시의 온도를 450℃로 한 것 이외에는, 실시예 1과 동일한 방법으로 실시하였다. 개질 후의 MSQ막의 비유전율은 3.8로, 비유전율의 저하는 인정되지 않았다.

Claims (7)

  1. 반도체 디바이스에 사용되는 저유전율막의 비유전율을 저하시키기 위한 개질제로서, 식(1)
    Figure 112009053248476-PCT00004
    (R은 C1~C4의 알킬기, n은 0~3의 정수)로 표시되는 규소 화합물을 유효성분으로서 함유하는, 저유전율막의 개질제.
  2. 제1항에 있어서,
    식(1)의 R이 메틸기인 저유전율막의 개질제.
  3. 제1항에 있어서,
    상기 규소 화합물이 아지도트리메틸실란((CH3)3SiN3), 아지도트리에틸실란((CH3CH2)3SiN3), 또는 아지도디메틸실란((CH3)2HSiN3)인 저유전율막의 개질제.
  4. 제1항 내지 제3항 중 어느 한 항에 있어서,
    추가적으로, 실란커플링제를 함유하는 저유전율막의 개질제.
  5. 반도체 디바이스에 사용되는 저유전율막에 대해, 제1항의 식(1)로 표시되는 규소 화합물을 함유하는 개질제를 20℃~300℃의 온도범위 내에서 접촉시키는 것을 포함하는, 개질된 저유전율막의 제조방법.
  6. 제5항에 있어서,
    상기 온도범위가 60℃~200℃인 개질된 저유전율막의 제조방법.
  7. 제5항 또는 제6항에 있어서,
    상기 접촉시키는 것을 대기에 폭로하지 않고 행하는 개질된 저유전율막의 제조방법.
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