KR20170077681A - Electostatic discharge circuit and display device having the same - Google Patents

Abstract

The present invention can improve the reliability of the electrostatic discharge circuit by reducing the turn-on delay time of the transistors by providing a compensation voltage equal to or higher than the threshold voltage to the gate terminal of the transistors passing the ground through the electrostatic discharge (ESD).

Description

TECHNICAL FIELD [0001] The present invention relates to an electrostatic discharge (ESD) circuit and a display device including the electrostatic discharge circuit.

The present invention relates to an electrostatic discharge circuit and a display device including the same.

2. Description of the Related Art Various flat panel displays (FPDs) have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such a flat panel display may be a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode (OLED) Display, and an electroluminescence device (ED).

An apparatus for displaying a desired image by adjusting the light transmittance of liquid crystal cells arranged in a matrix form in accordance with image signal information is provided with an image on a display panel using light emitted from a backlight unit. .

The display device using such a principle has a tendency of widening its application range due to features such as light weight, thinness, and low power consumption driving.

According to this trend, the display device is used in office automation equipment, audio / video equipment, and the like.

2. Description of the Related Art In recent years, a display device has been widely applied not only to a computer monitor, a television, a display device of a vehicle navigator system, and a portable display device such as a notebook computer or a mobile phone.

A general display device is provided with a data and timing control signal from an external system, and the timing control part provides reference voltages, data and control signals to the driving parts for driving the display panel.

A general display device includes an electrostatic discharge circuit that discharges electrostatic discharge (ESD) between the driving parts or the wirings of the display panel. A typical electrostatic discharge circuit includes transistors, and when static electricity (ESD) exceeding a certain voltage level or current level is input, the transistor is turned on and passed to ground. However, a typical display device has a problem in reliability of the electrostatic discharge circuit due to turn-on delay caused by the threshold voltage of the transistor.

An object of the present invention is to provide an electrostatic discharge circuit and a display device including the electrostatic discharge circuit.

An object of the present invention is to provide an electrostatic discharge circuit and a display device including the electrostatic discharge circuit that can improve the reliability of the electrostatic discharge circuit.

According to an aspect of the present invention, there is provided an electrostatic discharge (ESD) circuit including transistors for discharging an electrostatic discharge (ESD) between an input pad and an output line, By providing the back pressure portion to the terminal, it is possible to reduce the turn-on delay time of the transistors and to improve the driving portion damage by the electrostatic discharge (ESD).

That is, in the embodiment, it is possible to improve the reliability of the electrostatic discharge circuit by reducing the turn-on delay time of the transistors by providing a compensation voltage equal to or higher than the threshold voltage to the gate terminals of the transistors passing the ground through the electrostatic discharge (ESD).

The display device according to the present invention includes a first transistor for passing positive ESD through GND and a second transistor for passing negative ESD through a GND The display panel can be safely protected from static electricity (ESD) by reducing the turn-on delay time of the first and second transistors by providing a compensation voltage to the gate terminal.

Embodiments can improve the reliability of the electrostatic discharge circuit due to the fast turn-on delay time of the first and second transistors at the time of the introduction of the electrostatic discharge (ESD).

Embodiments can safely protect the driving circuit from electrostatic discharge (ESD) by the fast turn-on delay time of the first and second transistors at the time of the introduction of both electrostatic discharge (ESD), thereby improving the yield and productivity.

1 is a block diagram schematically showing a configuration of a display apparatus according to an embodiment of the present invention.
2 is a view of a display panel including an electrostatic discharge circuit in an embodiment.
3 is a diagram showing the configuration of the electrostatic discharge circuit according to the embodiment.
4 is a diagram showing an example of the electrostatic discharge circuit according to the embodiment.
5 is a graph showing the transistor turn-on delay time of the embodiment and the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of the invention to a person skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if a temporal posterior relationship is described by 'after', 'after', 'after', 'before', etc., 'May not be contiguous unless it is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

Fig. 1 is a block diagram schematically showing a configuration of a display apparatus according to an embodiment of the present invention, and Fig. 2 is a diagram of a display panel including an electrostatic discharge circuit in an embodiment.

1 and 2, the display device according to the embodiment of the present invention may include a display panel 2, a timing controller 8, a data driver 6, and a gate driver 4.

A liquid crystal display (LCD) is limited to the display device of the embodiment, but the present invention is not limited thereto. For example, the display device of another example may be a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode display (OLED), or an electrophoretic display (EPD).

The display panel 2 includes first and second glass substrates facing each other and liquid crystal molecules disposed between the first and second glass substrates. The display panel 2 has a matrix structure formed by intersecting the data lines D1 to Dm and the gate lines G1 to Gn and has m × n (m, n is a positive integer) liquid crystal cells Clc ).

The first glass substrate of the display panel 2 includes m data lines D1 to Dm, n gate lines G1 to Gn, data lines D1 to Dm and n gate lines G1 (TFT), a pixel electrode, and a storage capacitor (Cst), which are respectively connected to the transistors (TFT), and the like, which are located in intersecting regions of the pixels Gn to Gn.

On the second glass substrate of the display panel 2, a black matrix, a color filter, and a common electrode Vcom may be formed. Here, the common electrode (Vcom) may be changed in position according to a liquid crystal driving method. For example, the common electrode Vcom may be disposed on the second glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and may be in an IPS (In Plane Switching) mode and an FFS Field switching mode in which the pixel electrodes are arranged in a horizontal electric field driving mode.

The data driver 6 can latch the digital video data RGB by the control signal of the timing controller 8. [ The data driver 6 converts the digital video data into an analog positive / negative gamma compensation voltage to generate positive / negative data voltages and supplies the data voltages to the data lines D1 to Dm.

The gate driver 4 sequentially supplies gate signals having a pulse width of one horizontal period to the gate lines G1 to Gn by a control signal of the timing controller 8. [ The gate driver 4 can be formed directly on the first glass substrate simultaneously with the pixel array.

The timing controller 8 rearranges the digital video data (RGB) input from the external system in accordance with the display panel 2 and supplies it to the data driver 6.

The timing controller 8 receives a timing signal such as a vertical / horizontal synchronizing signal (Vsync, Hsync), a data enable signal and a clock signal (including a main clock signal such as CLK and MCLK) from an external system Control signals for controlling the operation timings of the data driver 6 and the gate driver 4 are generated.

The data timing control signal for controlling the data driver 6 includes a data start pulse (SSP), a source sampling clock (SSC), a polarity control signal (Pol) An SOE (Source Output Enable) signal, and the like. The data start pulse SSP controls the data sampling start timing of the data driver 6. [

The data sampling clock SSC is a clock signal that controls the sampling timing of data in the data driver 122 on the basis of the rising or falling edge. The data output enable signal SOE controls the output timing of the data driver 6. The polarity control signal POL controls the horizontal polarity inversion timing of the data voltage outputted from the data driver 6. [

The gate timing control signal for controlling the gate driver 4 includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like do.

The display panel 2 of the embodiment may include a display area AA in which an image is displayed and a non-display area NA in which no image is displayed. The non-display area NA may be disposed along the edge of the display area AA.

The non-display area NA may include a gate pad 12 connected to the gate lines G1 through Gn and a data pad 14 connected from the data lines D1 through Dm. The gate pad 12 may be defined as an input pad of the gadic driver 4 and the data pad 14 may be defined as an input pad of the data driver 6. [ The gate lines G1 to Gn and the data lines D1 to Dm may be defined as output lines.

The embodiment may include an electrostatic discharge circuit 20 disposed between the gate pad 12 and the gate lines G1 to Gn. Embodiments may include, but are not limited to, an electrostatic discharge circuit 20 disposed between the data pad 14 and the data lines D1 to Dm.

The electrostatic discharge circuit 20 passes positive static electricity ESD or negative static electricity ESD inputted from the gate pad 12 and the data pad 14 to a ground line . Here, the electrostatic discharge circuit 20 protects the display panel 2 from positive ESD or negative ESD to generate positive ESD or negative ESD, -) in the display panel 2 due to the electrostatic discharge (ESD) of the display panel 2.

The electrostatic discharge circuit 20 of the embodiment may include a first transistor that passes positive positive (ESD) static electricity to a ground (GND) line. The electrostatic discharge circuit 20 may include a second transistor for passing a negative electrostatic discharge (ESD) to a ground (GND) line. The first and second transistors may be MOS transistors, but the present invention is not limited thereto.

Embodiments can improve the response speed of the first and second transistors to secure electrostatic immunity from positive (ESD) or negative (ESD) static electricity. That is, the embodiment can improve the reliability of the electrostatic discharge circuit 20.

The electrostatic discharge circuit 20 of the embodiment will be described in detail with reference to Figs. 2 to 5.

FIG. 3 is a diagram showing the configuration of an electrostatic discharge circuit according to the embodiment, FIG. 4 is a diagram showing an example of the electrostatic discharge circuit according to the embodiment, Fig.

3 to 5, the electrostatic discharge circuit 20 of the embodiment may include a first transistor M1 for passing positive static electricity ESD to ground (GND). The electrostatic discharge circuit 20 of the embodiment may include a second transistor M2 for passing a negative electrostatic ESD to ground GND. The first and second transistors M1 and M2 may be MOS transistors. The first and second transistors M1 and M2 of the embodiment may be NMOS transistors, but are not limited thereto.

The embodiment may include a back pressure unit 21 connected to the gates of the first and second transistors M1 and M2. The back pressure unit 21 provides an arbitrary compensation voltage Vout to the gate terminals of the first and second transistors M1 and M2 so that the turn-on timing of the first and second transistors M1 and M2 And the like. The back pressure unit 21 may provide a compensation voltage Vout to the gate terminals of the first and second transistors M1 and M2 using an input voltage. The output terminal of the back pressure unit 21 may be connected to the gate terminals of the first and second transistors M1 and M2. Here, the gate terminals of the first and second transistors M1 and M2 may be connected to each other, but the present invention is not limited thereto.

The electrostatic discharge circuit 20 may include a second diode D2 between a gate terminal of the first transistor M1 and an output terminal of the back pressure unit 21. [ The electrostatic discharge circuit 20 may include a third diode D3 between a gate terminal of the second transistor M2 and an output terminal of the back pressure unit 21. [ The second and third diodes D2 and D3 may include a function of protecting the back pressure unit 21 from positive ESD or negative ESD.

The electrostatic discharge circuit 20 may include a first diode D1 between the gate terminal of the first transistor M1 and the first node N1. The first node N1 may be disposed on the output line of the gate pad 12 or the data pad 14 and the gate lines G1 to Gn or the data lines D1 to Dm. The first diode D1 may include a reverse current prevention function.

The electrostatic discharge circuit 20 may include a fourth diode D4 between the gate terminal of the second transistor D2 and the ground GND. Here, the drain terminal of the second transistor M2 may be coupled to the second node N2. The second node N2 may be disposed on the output line of the first node N1 and the gate lines G1 to Gn or the data lines D1 to Dm. The fourth diode D4 may include a reverse current prevention function.

The back pressure unit 21 may have a voltage level lower than a threshold voltage (MOS Vth) of the first and second transistors M1 and M2 at the gate terminals of the first and second transistors M1 and M2 . For example, the compensation voltage Vout of the back pressure unit 21 may be 50% or more of the threshold voltage (MOS Vth) of the first and second transistors M1 and M2. More specifically, the compensation voltage Vout of the back pressure portion 21 may be 80% of the threshold voltage (MOS Vth) of the first and second transistors M1 and M2. It is difficult to improve the turn-on delay time of the first and second transistors M1 and M2 when the compensation transfer voltage Vout has a voltage level lower than 50% of the threshold voltage MOS Vth. If the compensated transfer (Vout) has a voltage level exceeding 80% of the threshold voltage (MOS Vth), the reliability of the electrostatic discharge circuit 20 may be degraded.

The back pressure unit 21 may include a compensation voltage control unit 23, a third transistor M3, an inductor L, a fifth diode D5, and a capacitor C. The back pressure unit 21 may be connected to the third node N3 between the first and second nodes N1 and N2.

The compensation voltage controller 23 generates a reference voltage for generating the compensation voltage Vout using the input voltage. Here, the voltage level of the input voltage does not correspond to the voltage level of the compensation voltage Vout.

The inductor L may include a function of storing a current of an input voltage and increasing the voltage of the third transistor M3 to a compensation voltage Vout that is output when the third transistor M3 is turned on. The inductor L may be connected to a drain terminal of the third transistor M3.

The fifth diode D5 may include a reflux diode function. That is, the fifth diode D5 passes the impulse voltage due to the reverse electromotive force of the inductor L when the third transistor M3 is turned off. That is, the fifth diode D5 may be connected in parallel with the third transistor M3 to protect the third transistor M3.

The capacitor C may include a function of smoothing the compensation voltage Vout. The capacitor C may be connected in parallel with the fifth diode D5.

The compensation voltage controller 23 compensates the voltage of the first node N1 from the second node N2 connected to the gate terminals of the first and second transistors M1 and M2 and the third node N3 between the first node N1 The voltage Vout may be fed back through the fourth node N4 to maintain a constant compensation voltage Vout. The fourth node N4 may be connected to a fifth node N5 which is defined as an output terminal of the back pressure unit 21 connected to gate terminals of the first and second transistors M1 and M2.

The back pressure section 21 of the embodiment is limited to the configuration including the compensation voltage control section 23, the third transistor M3, the inductor L, the fifth diode D5 and the capacitor C. However, But is not limited thereto.

In the embodiment, a compensating voltage of 80% of the threshold voltage (MOS Vth) voltage level of the first and second transistors M1 and M2 is applied to the gate terminals of the first and second transistors M1 and M2 from the back- On delay time t2 which is earlier than the turn-on delay time t1 of the general first and second transistors M1 and M2 is provided. Therefore, the embodiment can reduce the turn-on delay time of the first and second transistors M1 and M2 to prevent the display panel 2 from being positive ESD or negative ESD, Can be safely protected.

The embodiment can simplify the configuration of the driving circuit by keeping the compensation voltage Vout constant at the gate terminals of the first and second transistors M1 and M2 by using the input voltage.

Table 1 shows the turn-on delay times of the first and second transistors M1 and M2 at the time of ESD input.

Gate terminal voltage The first and second transistor turn-on delay times Typical electrostatic discharge circuit 0V 7.2 Example 1 1V 6 ㎱ Example 2 2V 4.2 Example 3 3V 3.2

In Embodiments 1 to 3, the compensation voltage Vout is 1 V to 3 V, and the threshold voltage (MOS Vth) of the first and second transistors M1 and M2 may be 4 V, but the present invention is not limited thereto. For example, the threshold voltage (MOS Vth) of the first and second transistors M1 and M2 may be changed and the compensation voltage Vth may be changed according to the threshold voltage (MOS Vth) of the first and second transistors M1 and M2 Vout) can also be changed.

Embodiments 1 to 3 can achieve a fast turn-on delay time of up to 55% compared to a conventional electrostatic discharge circuit.

A compensating voltage Vout of 50% or more of the threshold voltage (MOS Vth) of the first and second transistors M1 and M2 is provided to the gate terminal so that the voltage of the first and second transistors M1 and M2 It is possible to securely protect the display panel 2 from positive static electricity (ESD) or negative static electricity (ESD) by reducing the turn-on delay time.

The embodiment is advantageous in that the positive turn-on delay time of the first and second transistors M1 and M2 at the time of positive (ESD) or negative (ESD) It is possible to safely protect the driving circuit from electrostatic (ESD) or negative (-) static electricity (ESD), thereby improving yield and productivity.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments can be combined and modified by other persons having ordinary skill in the art to which the embodiments belong. Accordingly, the contents of such combinations and modifications should be construed as being included in the scope of the embodiments.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It can be seen that the modification and application of branches are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

20: Electrostatic discharge circuit
21:
23: compensation transfer control unit
M1: first transistor
M2: second transistor
M3: third transistor

Claims (7)

Input pad;
An output line coupled to the input pad;
A first transistor coupled to a first node adjacent to the input pad;
A second transistor coupled to a second node adjacent to the output line; And
And a back pressure section connected to a third node between the first and second nodes, wherein the back pressure section provides a constant compensation voltage to the gate terminals of the first and second transistors.
The method according to claim 1,
Wherein the compensation voltage has a voltage level of at least 50% of a threshold voltage of the first and second transistors.
The method according to claim 1,
Wherein the compensation voltage has a voltage level of 80% of a threshold voltage of the first and second transistors.
The method according to claim 1,
A first diode connected to the gate terminal of the first transistor and the first node; And
And a fourth diode connected between the gate terminal of the second transistor and ground.
The method according to claim 1,
A second diode connected between the gate terminal of the first transistor and the back pressure portion; And
And a third diode coupled to the gate terminal of the second transistor and the backpressure portion.
The method according to claim 1,
The back-
A compensation voltage control unit connected to the third node;
An inductor coupled to the third node;
A third transistor that is turned on by a control signal of the compensation low voltage control unit;
A fifth diode connected in parallel with the third transistor; And
And a capacitor connected in parallel with the fifth diode.
An electrostatic discharge circuit according to any one of claims 1 to 6; And
And a display panel in which an image is displayed by a drive signal input from the output line.

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