KR910013541A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

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Publication number
KR910013541A
KR910013541A KR1019900021725A KR900021725A KR910013541A KR 910013541 A KR910013541 A KR 910013541A KR 1019900021725 A KR1019900021725 A KR 1019900021725A KR 900021725 A KR900021725 A KR 900021725A KR 910013541 A KR910013541 A KR 910013541A
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South Korea
Prior art keywords
layer
metal layer
metal
amorphous silicon
contact film
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KR1019900021725A
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KR100191359B1 (ko
Inventor
기예스베르투스 마티아스 욘케르스 알렉산데르
앨런 씸즈 크리스토퍼
고던 해럴드
스톨메이예르 안드레
Original Assignee
프레데릭 얀 스미트
엔.브이.필립스 글로아이람펜파브리켄
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Publication of KR910013541A publication Critical patent/KR910013541A/ko
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Publication of KR100191359B1 publication Critical patent/KR100191359B1/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음.

Description

반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명에 따르는 방법의 실시예에 따라 제조의 연속적인 단계에서 반도체 장치를 도식적으로 도시한 단면도.

Claims (4)

  1. 필드 산화물 형태의 상기 형태에 인접한 실리콘 영역을 포함하는 반도체 본체를 가지며, 실리콘의 도체 형태가 상기 본체의 표면상에 제공되며, 그런후 상기 표면이 금속 층으로 덮이며, 그리고 상호 접속되는 부분은 마스크에 의한 무결정 실리콘 층으로 덮여지고, 그런 후 상기 금속 층이 질소를 함유한 기체 속에서 열처리를 함으로써 적어도 부분적으로 금속 실리사이드로 변환시키며 그리고 절연층은 모든 표면상에 제공되고, 표면상에서 절연층은 평평화되고, 접촉 막은 평평화된 층속에 제공되고, 그리고 결과적으로 금속화는 표면상에 그리고 접촉막에 제공되는 반도체 본체를 가지며, 상기 무결정 실리콘 층이 반도체 형태 위에 형성된 적어도 접촉막 아래의 상기 마스크에 의해 금속층상에 제공되는 것을 특징으로 하는 반도체 장치를 제조하는 방법.
  2. 제1항에 있어서, 상기 무결정 실리콘 층이 모든 두께를 통해 금속 실리사이드로 변환되는 것을 특징으로 하는 방법.
  3. 제1항 또는 2항에 있어서, 상기 무결정 층이 금속 층 위에 위치한 모든 접촉막 아래에 제공되는 것을 특징으로 하는 방법.
  4. 선행항 중 어느 한 항에 있어서, 티타늄의 금속 층이 제공되는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900021725A 1989-12-27 1990-12-26 반도체 장치의 제조방법 Expired - Fee Related KR100191359B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8903158 1989-12-27
NL8903158A NL8903158A (nl) 1989-12-27 1989-12-27 Werkwijze voor het contacteren van silicidesporen.

Publications (2)

Publication Number Publication Date
KR910013541A true KR910013541A (ko) 1991-08-08
KR100191359B1 KR100191359B1 (ko) 1999-06-15

Family

ID=19855830

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021725A Expired - Fee Related KR100191359B1 (ko) 1989-12-27 1990-12-26 반도체 장치의 제조방법

Country Status (6)

Country Link
US (1) US5081065A (ko)
EP (1) EP0435392B1 (ko)
JP (1) JPH088226B2 (ko)
KR (1) KR100191359B1 (ko)
DE (1) DE69022836T2 (ko)
NL (1) NL8903158A (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834368A (en) * 1992-02-13 1998-11-10 Nec Corporation Integrated circuit with a metal silicide film uniformly formed
EP0567815B1 (de) * 1992-04-29 1998-07-15 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
US5313084A (en) * 1992-05-29 1994-05-17 Sgs-Thomson Microelectronics, Inc. Interconnect structure for an integrated circuit
US5256597A (en) * 1992-09-04 1993-10-26 International Business Machines Corporation Self-aligned conducting etch stop for interconnect patterning
JP3067433B2 (ja) * 1992-12-04 2000-07-17 キヤノン株式会社 半導体装置の製造方法
US5268330A (en) * 1992-12-11 1993-12-07 International Business Machines Corporation Process for improving sheet resistance of an integrated circuit device gate
JPH06349826A (ja) * 1993-04-13 1994-12-22 Toshiba Corp 半導体装置およびその製造方法
US5322809A (en) * 1993-05-11 1994-06-21 Texas Instruments Incorporated Self-aligned silicide process
US5342798A (en) * 1993-11-23 1994-08-30 Vlsi Technology, Inc. Method for selective salicidation of source/drain regions of a transistor
JP2630290B2 (ja) * 1995-01-30 1997-07-16 日本電気株式会社 半導体装置の製造方法
DE59506590D1 (de) * 1995-05-23 1999-09-16 Siemens Ag Halbleiteranordnung mit selbstjustierten Kontakten und Verfahren zu ihrer Herstellung
US5631188A (en) * 1995-12-27 1997-05-20 Taiwan Semiconductor Manufacturing Company Ltd. Low voltage coefficient polysilicon capacitor
KR100642648B1 (ko) * 2005-09-13 2006-11-10 삼성전자주식회사 실리사이드막들을 갖는 콘택 구조체, 이를 채택하는반도체소자, 및 이를 제조하는 방법들

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57192073A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor device
US4873204A (en) * 1984-06-15 1989-10-10 Hewlett-Packard Company Method for making silicide interconnection structures for integrated circuit devices
US4708767A (en) * 1984-10-05 1987-11-24 Signetics Corporation Method for providing a semiconductor device with planarized contacts
US4788160A (en) * 1987-03-31 1988-11-29 Texas Instruments Incorporated Process for formation of shallow silicided junctions
EP0296718A3 (en) * 1987-06-26 1990-05-02 Hewlett-Packard Company A coplanar and self-aligned contact structure
WO1989011733A1 (en) * 1988-05-24 1989-11-30 Micron Technology, Inc. Alpha shielded tisi2 local interconnects

Also Published As

Publication number Publication date
EP0435392B1 (en) 1995-10-04
DE69022836D1 (de) 1995-11-09
DE69022836T2 (de) 1996-05-15
US5081065A (en) 1992-01-14
JPH04137622A (ja) 1992-05-12
NL8903158A (nl) 1991-07-16
EP0435392A1 (en) 1991-07-03
KR100191359B1 (ko) 1999-06-15
JPH088226B2 (ja) 1996-01-29

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