KR930001480A - 트랜치 베리드 ldd mosfet의 구조 및 제조 방법 - Google Patents

트랜치 베리드 ldd mosfet의 구조 및 제조 방법 Download PDF

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KR930001480A
KR930001480A KR1019910011039A KR910011039A KR930001480A KR 930001480 A KR930001480 A KR 930001480A KR 1019910011039 A KR1019910011039 A KR 1019910011039A KR 910011039 A KR910011039 A KR 910011039A KR 930001480 A KR930001480 A KR 930001480A
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South Korea
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gate
nitride film
oxide
oxide film
ldd
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KR1019910011039A
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KR940002406B1 (ko
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이혁재
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문정환
금성일렉트론 주식회사
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/025Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음

Description

트랜치 베리드 LDD MOSFET의 구조 및 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 (가) 내지 (사)는 본 발명에 따른 트랜치 베리드 LDD MOSFET 제조공정도.
제3도는 본 발명에 따른 트랜치 베리드 LDD MOSFET 구조도.

Claims (2)

  1. 트랜치구조의 게이트를 갖는 LDD MOSFET에 있어서, 소오스/드레인 영역(19)에 n-LDD(17)영역이 접하고, 그 n-LDD(17)영역이 Vtn이온주입층인 할로영역(15)에 의해 포켓팅되어 그 할로영역(15)이 트랜치 게이트(16)의 게이트옥사이드(14)와 접하며, 상기 n-LDD(17) 및 할로영역(15)상부에 게이트옥사이드인 산화막(12-2) 및 질화막(13-2)이 형성되어 게이트(16)와 접하고, 그 게이트(16)의 양측에 상기 질화막(13-2) 및 사이드웰(18)이 형성된 구조로 된 것을 특징으로 하는 트랜치 베리드 LDD MOSFET의 구조.
  2. 로커스공정후 기판(11)위에 산화막(12-1) 및 질화막(13-1)을 순차증착하고, 그 질화막(13-1) 및 산화막(12-1)을 마스크를 이용하여 에치시켜 할로이온주입을 한 후 상기 산화막(12-1)위의 잔여 질화막(13-1)을 제거하며, 이후 베이스옥사이드(12-2)를 성장시키고 그 위에 질화막(13-2) 및 산화막(12-3)을 순차증착하여 마스크를 이용해 상기 산화막(12-3) 및 질화막(13-2)을 에치백하고, 베이스옥사이드(12-2)를 에치한 후 드러난 기판(11)을 트랜치게이트를 위한 에치를 하며, 상기 산화막(12-3) 및 질화막(13-2)에치시 형성된 사이드웰 산화막(12-3)을 에치한 후 게이트옥사이드(14)를 성장시키고, 그 위에 폴리게이트(4)를 증착시켜 에치백에 의한 패터닝한 후, 상기 질화막(13-2) 외측의 상기 산화막(12-1)을 에치시키고, 상기 게이트(4)위에 캡 질화막(13-3)을 형성시킨 후 n-이온주입하여 할로이온주입영역(15)을 정의하면, 사이드웰(18)을 형성시킨 후 n+이온주입하여 소오스/드레인(19)영역을 형성함과 아울러 LDD(17)영역을 정의하고, 이후 절연막(20) 및 메탈(21)공정으로 제조하는 것을 특징으로 하는 트랜치 베리드 LDD MOSFET의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019910011039A 1991-06-29 1991-06-29 트랜치 베리드 ldd mosfet의 구조 및 제조방법 Expired - Fee Related KR940002406B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910011039A KR940002406B1 (ko) 1991-06-29 1991-06-29 트랜치 베리드 ldd mosfet의 구조 및 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910011039A KR940002406B1 (ko) 1991-06-29 1991-06-29 트랜치 베리드 ldd mosfet의 구조 및 제조방법

Publications (2)

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KR930001480A true KR930001480A (ko) 1993-01-16
KR940002406B1 KR940002406B1 (ko) 1994-03-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6267497B1 (en) 1998-04-22 2001-07-31 Myng-Sup Rhee Device for producing feed stuff or organic fertilizer from edible waste material through low temperature, natural fermentation and drying process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6267497B1 (en) 1998-04-22 2001-07-31 Myng-Sup Rhee Device for producing feed stuff or organic fertilizer from edible waste material through low temperature, natural fermentation and drying process

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Publication number Publication date
KR940002406B1 (ko) 1994-03-24

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