KR970052997A - 바이폴라 트랜지스터 제조 방법 - Google Patents

바이폴라 트랜지스터 제조 방법

Info

Publication number
KR970052997A
KR970052997A KR1019960074077A KR19960074077A KR970052997A KR 970052997 A KR970052997 A KR 970052997A KR 1019960074077 A KR1019960074077 A KR 1019960074077A KR 19960074077 A KR19960074077 A KR 19960074077A KR 970052997 A KR970052997 A KR 970052997A
Authority
KR
South Korea
Prior art keywords
forming
region
bipolar transistor
polycrystalline silicon
indium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1019960074077A
Other languages
English (en)
Inventor
토마스 에드워드 햄
씨 키지리얄리아이식
Original Assignee
웨이스 엘리
루슨트테크놀로지스인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 웨이스 엘리, 루슨트테크놀로지스인코포레이티드 filed Critical 웨이스 엘리
Publication of KR970052997A publication Critical patent/KR970052997A/ko
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/225—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of a molecular ion, e.g. decaborane
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors

Landscapes

  • Bipolar Transistors (AREA)

Abstract

우수한 동작 특성을 갖는 바이폴라 트랜지스터의 베이스를 제조하는데 인듐도핑이 사용된다.

Description

바이폴라 트랜지스터 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명의 실시예의 단면도.

Claims (4)

  1. 바이폴라 트랜지스터를 제조하는 방법에 있어서, 반도체 기판에 제1의 n도핑 영역을 형성하여 콜렉터 영역을 형성하는 단계와, 상기 n도핑 영역에 인듐 이온을 주입하여 베이스 영역을 형성하는 단계와, 상기 베이스 영역과 접촉하는 에미터 영역을 형성하는 단계를 포함하는 바이폴라 트랜지스터 제조 방법.
  2. 제1항에 있어서, 상기 인듐은 20-200KeV의 에너지로 주입되는 바이폴라 트랜지스터 제조 방법.
  3. 제1항에 있어서, 상기 인듐 1212내지 1015cm-2의 도즈량으로 주입되는 바이폴라 트랜지스터 제조 방법.
  4. 제1항에 있어서, 상기 에미터 영역은, 상기 기판상에 패턴화된 옥사이드 층을 형성하는 단계로, 이 패턴화된 층은 상기 베이스 영역을 노광하는 개구를 상기 형성 단계와, 상기 개구내에 다결정 실리콘을 증착 및 도핑하는 단계와, 상기 다결정 실리콘의 외부로 그리고 상기 기판내부로 도펀트가 유도되도록 상기 도핑된 다결정 실리콘을 가열하여 에미터를 형성하는 단계에 의해 형성되는 바이폴라 트랜지스터 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960074077A 1995-12-29 1996-12-27 바이폴라 트랜지스터 제조 방법 Abandoned KR970052997A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/581,665 US5681763A (en) 1995-12-29 1995-12-29 Method for making bipolar transistors having indium doped base
US8/581,665 1995-12-29

Publications (1)

Publication Number Publication Date
KR970052997A true KR970052997A (ko) 1997-07-29

Family

ID=24326083

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960074077A Abandoned KR970052997A (ko) 1995-12-29 1996-12-27 바이폴라 트랜지스터 제조 방법

Country Status (4)

Country Link
US (1) US5681763A (ko)
JP (1) JPH09186171A (ko)
KR (1) KR970052997A (ko)
TW (1) TW363227B (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087683A (en) * 1998-07-31 2000-07-11 Lucent Technologies Silicon germanium heterostructure bipolar transistor with indium doped base
SE517434C3 (sv) * 1999-10-08 2002-08-07 Ericsson Telefon Ab L M Bipolär högfrekvenskiseltransistor och förfarande för att förbättra karakeristiken för en sådan transistor genom tillägg av indium i transistors bas
US6822314B2 (en) 2002-06-12 2004-11-23 Intersil Americas Inc. Base for a NPN bipolar transistor
KR100466594B1 (ko) * 2002-06-29 2005-01-24 주식회사 팬택앤큐리텔 연성회로기판의 가이드장치 및 이를 구비한 이동 단말기
US6830982B1 (en) * 2002-11-07 2004-12-14 Newport Fab, Llc Method for reducing extrinsic base resistance and improving manufacturability in an NPN transistor
US7592642B1 (en) 2003-09-25 2009-09-22 T-Ram Semiconductor, Inc. Thyristor-based semiconductor device with indium-carbon implant and method of fabrication
US7195959B1 (en) 2004-10-04 2007-03-27 T-Ram Semiconductor, Inc. Thyristor-based semiconductor device and method of fabrication
DE10357796B4 (de) * 2003-12-10 2007-09-27 Infineon Technologies Ag Stossstromfestes Leistungshalbleiterbauelement und Verfahren zu seiner Herstellung
KR100835113B1 (ko) 2006-08-22 2008-06-03 동부일렉트로닉스 주식회사 바이폴라 접합 트랜지스터 및 그 제조 방법과, 이를 갖는씨모스 이미지 센서 및 그 제조 방법
EP2499927A1 (en) 2011-03-15 2012-09-19 Lien-Chun Tai Decorated lacing

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5284783A (en) * 1988-10-27 1994-02-08 Fujitsu Limited Method of fabricating a heterojunction bipolar transistor
JPH07142419A (ja) * 1993-11-15 1995-06-02 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US5681763A (en) 1997-10-28
TW363227B (en) 1999-07-01
JPH09186171A (ja) 1997-07-15

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