KR970076830A - The bit line voltage control circuit of the memory device - Google Patents

The bit line voltage control circuit of the memory device Download PDF

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Publication number
KR970076830A
KR970076830A KR1019960015944A KR19960015944A KR970076830A KR 970076830 A KR970076830 A KR 970076830A KR 1019960015944 A KR1019960015944 A KR 1019960015944A KR 19960015944 A KR19960015944 A KR 19960015944A KR 970076830 A KR970076830 A KR 970076830A
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South Korea
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bit line
line voltage
signal
voltage control
memory device
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KR1019960015944A
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Korean (ko)
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한규한
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김광호
삼성전자 주식회사
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Publication of KR970076830A publication Critical patent/KR970076830A/en
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Abstract

본 발명은 메모리 장치의 비트라인전압 제어회로에 관한 것으로서, 로우 어드레스 스트로브 신호에 응답하여 인에이블 되는 어드레스 스트로브 마스터 신호와 등화 제어신호에 응답하여 액티브 초기구간을 검출하고 검출된 신호를 제어신호로 발생하는 액티브 초기구간 검출수단과, 상기 액티브 초기구간 검출수단에 응답하여 제1비트라인 전압을 더 낮은 제2비트라인전압으로 다운시키는 비트라인 구동전압 제어수단과, 상기 등화 제어신호에 응답하여 액티브구간 초기에는 상기 비트라인 구동전압 제어수단으로부터 제공되는 제1 및 제2비트라인 구동전압에 의해 상기 제1, 제2비트라인을 등화시키기 위한 등화회로부를 구비하는 것을 특징으로 한다.The present invention relates to a bit line voltage control circuit of a memory device, which detects an active initial period in response to an address strobe master signal and an equalization control signal which are enabled in response to a row address strobe signal and generates a detected signal as a control signal Bit line drive voltage control means for decreasing a first bit line voltage to a second lower bit line voltage in response to the active initial period detection means; And an equalizing circuit for initially equalizing the first and second bit lines by the first and second bit line driving voltages provided from the bit line driving voltage control means.

따라서, 상술한 바와 같이 본 발명에서는 종래의 비트라인 전압 발생부의 제한을 개선하기 위해 비트라인전압 제어수단을 설치하고 액티브 초기구간 검출수단에서 발생하는 제어신호의 액티브 초기에 비트라인 구동전압 제어수단을 통해 제1, 제2비트라인 전압을 양 비트라인 전압차의 절반레벨 이하로 낮추고, 센스증폭기(미도시)가 감지할 수 있는 비트라인 전압 마진을 비트라인전압 감소분 만큼 증대시킴으로써, 저전압원 마진이 향상되어, 저전압원에서 동작 가능한 대용량과 저소비전력의 메모리 장치의 구현을 가능하게 한다.As described above, in the present invention, the bit line voltage control means is provided to improve the limit of the conventional bit line voltage generator, and the bit line voltage control means is activated at the active initial stage of the control signal generated by the active initial section detection means By lowering the first and second bit line voltages to less than half the level of both bit line voltage differences and increasing the bit line voltage margin that the sense amplifier (not shown) can sense by the bit line voltage reduction, Thereby enabling implementation of a large-capacity and low-power-consumption memory device operable in a low-voltage source.

Description

메모리 장치의 비트라인전압 제어회로The bit line voltage control circuit of the memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 의한 메모리 장치의 비트라인전압 제어회로의 구성을 나타낸 회로도.FIG. 3 is a circuit diagram showing a configuration of a bit line voltage control circuit of a memory device according to the present invention; FIG.

Claims (3)

로우 어드레스 스트로브 신호에 응답하여 인에이블 되는 로우 어드레스 스트로브 마스터 신호와 등화 제어신호에 응답하여 액티브 초기구간을 검출하고 검출된 신호를 제어신호로 발생하는 액티브 초기구간 검출수단; 상기 액티브 초기구간 검출수단에 응답하여 제1비트라인 구동전압을 더 낮은 제2비트라인 구동전압으로 다운시키는 비트라인 구동전압 제어수단; 및 상기 등화 제어신호에 응답하여 액티브구간 초기에는 상기 비트라인 구동전압 제어수단으로부터 제공되는 제1 및 제2비트라인 구동전압에 의행 상기 제1, 제2비트라인을 등화시키기 위한 등화회로부를 구비하는 것을 특징으로 하는 메모리 장치의 비트라인전압 제어회로.Active initial section detection means for detecting an active initial section in response to a row address strobe master signal and an equalization control signal enabled in response to a row address strobe signal and generating a detected signal as a control signal; A bit line drive voltage control means for decreasing a first bit line drive voltage to a second lower bit line drive voltage in response to the active initial section detection means; And an equalization circuit unit for equalizing the first and second bit lines to the first and second bit line driving voltages provided from the bit line driving voltage control unit in the active period in response to the equalization control signal And the bit line voltage control circuit of the memory device. 제1항에 있어서, 상기 비트라인 구동전압 제어수단은 제1비트라인 구동전압과 제2비트라인 구동전압 사이에 연결되어 상기 액티브 초기구간 검출신호에 응답하여 액티브 초기구간에만 턴온되는 모스 트랜지스터로 구성된 것을 특징으로 하는 메모리 장치의 비트라인전압 제어회로.2. The semiconductor memory device according to claim 1, wherein the bit line driving voltage control means comprises a MOS transistor connected between a first bit line driving voltage and a second bit line driving voltage and being turned on only in an active initial period in response to the active initial section detecting signal And the bit line voltage control circuit of the memory device. 제1항에 있어서, 상기 액티브 초기구간 검출수단은 상기 로우 어드레스 마스터신호와 등화 제어신호를 부정 논리곱하는 낸드게이트와 상기 낸드게이트의출력을 반전하여 상기 액티브 제어신호를 발생하는 인버터로 구성된 것을 특징으로 하는 메모리장치의 비트라인전압 제어회로.2. The semiconductor memory device according to claim 1, wherein the active initial section detecting means comprises a NAND gate for negatively ANDing the row address master signal and the equalization control signal, and an inverter for inverting the output of the NAND gate to generate the active control signal Bit line voltage control circuit of the memory device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960015944A 1996-05-14 1996-05-14 The bit line voltage control circuit of the memory device Withdrawn KR970076830A (en)

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KR1019960015944A KR970076830A (en) 1996-05-14 1996-05-14 The bit line voltage control circuit of the memory device

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KR1019960015944A KR970076830A (en) 1996-05-14 1996-05-14 The bit line voltage control circuit of the memory device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100483026B1 (en) * 2002-07-11 2005-04-15 주식회사 하이닉스반도체 Semiconductor memory device
KR100761403B1 (en) * 2006-09-29 2007-09-27 주식회사 하이닉스반도체 Bit line equalization circuit and bit line equalization method of a memory device.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100483026B1 (en) * 2002-07-11 2005-04-15 주식회사 하이닉스반도체 Semiconductor memory device
KR100761403B1 (en) * 2006-09-29 2007-09-27 주식회사 하이닉스반도체 Bit line equalization circuit and bit line equalization method of a memory device.

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Patent event code: PA01091R01D

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Patent event date: 19960514

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