KR970077196A - METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR - Google Patents

METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR Download PDF

Info

Publication number
KR970077196A
KR970077196A KR1019960015575A KR19960015575A KR970077196A KR 970077196 A KR970077196 A KR 970077196A KR 1019960015575 A KR1019960015575 A KR 1019960015575A KR 19960015575 A KR19960015575 A KR 19960015575A KR 970077196 A KR970077196 A KR 970077196A
Authority
KR
South Korea
Prior art keywords
film
forming
pattern
metal
photoresist pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019960015575A
Other languages
Korean (ko)
Inventor
여정호
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960015575A priority Critical patent/KR970077196A/en
Publication of KR970077196A publication Critical patent/KR970077196A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H10P76/2043—Photolithographic processes using an anti-reflective coating

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

실리콘질화막을 반사방지막으로 이용하는 반도체 장치의 금속 배선 형성방법에 곤하여 개시한다. 본 발명은 반도체 기판 상에 실리콘화막을 형성하는 단계와, 상기 실리콘산화막 상에 제1금속막을 형성하는 단계와, 상기 제1금속막상에 실리콘질화막(SiN)으로 반사방지막을 형성하는 단계와, 상기 반사방지막 상에 제1포토레지스트 패턴을 형성하는 단계와, 상기 제1포토지시스트 패턴을 마스크로 상기 반사방지막 및 제1금속막을 식각하여 홀을 갖는 제1반사방지막 패턴 및 제1금속막 패턴을 형성하는 단계와, 상기 제1포토레지스트 패턴을 제거하는 단계와, 상기 기판의 전면에 상기 홀을 매립하도록 실리콘질화막으로 보호막을 형성하는 단계와, 상기 보호막 상에 제2포토레지스트 패턴을 형성하는 단계와, 상기 제2포토레지스트 패턴을 마스크로 상기 보호막 및 제1반사방지막 패턴을 순차적으로 식각하여 보호막 패턴 및 제2반사방지막 패턴을 형성하는 단계와, 상기 제2포토레지스트 패턴을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성방법을 제공한다. 본 발명은 반사방지막을 실리콘질화막으로 형성하고, 와이어 본딩을 위한 반사방지막의 식각을 보호막의 식각시 순차적으로 식각하여 공정을 단순하게 할 수 있다.And a method for forming a metal wiring of a semiconductor device using a silicon nitride film as an antireflection film. The present invention provides a method of manufacturing a semiconductor device, comprising: forming a siliconized film on a semiconductor substrate; forming a first metal film on the silicon oxide film; forming an antireflection film on the first metal film with a silicon nitride film (SiN) Forming a first photoresist pattern on the antireflection film; etching the antireflection film and the first metal film using the first photoresist pattern as a mask to form a first antireflection film pattern having holes and a first metal film pattern, Forming a protective film with a silicon nitride film on the entire surface of the substrate so as to fill the hole, forming a second photoresist pattern on the protective film, And forming a protective film pattern and a second anti-reflective film pattern by sequentially etching the protective film and the first anti-reflective film pattern using the second photoresist pattern as a mask It provides the steps and, the second photoresist to form metal wiring of a semiconductor device characterized in that it comprises a step of removing the pattern. The present invention can simplify the process by forming the antireflection film as a silicon nitride film and sequentially etching the antireflection film for wire bonding at the time of etching the protective film.

Description

반도체장치의 금속 배선 형성방법METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제5도 내지 제7도는 본 발명에 의한 반도체 장치의 금속 배선 형성방법을 설명하기 위하여 도시한 단면도들이다.5 to 7 are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device according to the present invention.

Claims (1)

반도체 기판 상에 실리콘산화막을 형성하는 단계; 상기 실리콘산화막 상에 제1금속막을 형성하는 단계; 상기 제1금속막상에 실리콘질화막(SiN)으로 반사방지막을 형성하는 단계; 상기 반사방지막 상에 제1포토레지스트 패턴을 형성하는 단계; 상기 제1포토레지스트 패턴을 마스크로 상기 반사방지막 및 제1금속막을 식각하여 홀을 갖는 제1반사방지막 패턴 및 제1금속막 패턴을 형성하는 단계; 상기 제1포토레지스트 패턴을 제거하는 단계; 상기 기판의 전면에 상기 홀을 매립하도록 실리콘질화막으로 보호막을 형성하는 단계; 상기보호막 상에 제2포토레지스트 패턴을 형성하는 단계; 상기 제2포토레지스트 패턴을 마스크로 상기 보호막및 제1반사방지막 패턴을 순차적으로 식각하여 보호막 패턴 및 제2반사방지막 패턴을 형성하는 단계; 및 상기제2포토레지스트 패턴을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성방법..Forming a silicon oxide film on a semiconductor substrate; Forming a first metal film on the silicon oxide film; Forming an anti-reflection film with a silicon nitride film (SiN) on the first metal film; Forming a first photoresist pattern on the anti-reflection film; Forming a first antireflection film pattern and a first metal film pattern having holes by etching the antireflection film and the first metal film using the first photoresist pattern as a mask; Removing the first photoresist pattern; Forming a protective film with a silicon nitride film on the entire surface of the substrate to fill the hole; Forming a second photoresist pattern on the protective film; Forming a protective film pattern and a second anti-reflective film pattern by sequentially etching the protective film and the first anti-reflective film pattern using the second photoresist pattern as a mask; And removing the second photoresist pattern. A method of forming a metal wiring of a semiconductor device, ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임※ Note: It is disclosed by the contents of the first application.
KR1019960015575A 1996-05-11 1996-05-11 METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR Withdrawn KR970077196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960015575A KR970077196A (en) 1996-05-11 1996-05-11 METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960015575A KR970077196A (en) 1996-05-11 1996-05-11 METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR

Publications (1)

Publication Number Publication Date
KR970077196A true KR970077196A (en) 1997-12-12

Family

ID=66220013

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960015575A Withdrawn KR970077196A (en) 1996-05-11 1996-05-11 METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR

Country Status (1)

Country Link
KR (1) KR970077196A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100619398B1 (en) * 2003-12-26 2006-09-11 동부일렉트로닉스 주식회사 Reticle manufacturing method with anti-reflection film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100619398B1 (en) * 2003-12-26 2006-09-11 동부일렉트로닉스 주식회사 Reticle manufacturing method with anti-reflection film

Similar Documents

Publication Publication Date Title
KR950034678A (en) A method for forming a conductive connection in an integrated circuit and a conductive member in the circuit
KR970003459A (en) Method of forming via hole in semiconductor device
KR970077196A (en) METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR
KR970067640A (en) Method for forming a metal layer of a semiconductor
KR980005933A (en) Method for forming bonding pads of semiconductor devices
KR0137619B1 (en) Manufacturing method of semiconductor device
KR950021126A (en) Metal wiring layer formation method
KR970072316A (en) Method for forming multiple metal layers of semiconductor devices
KR970072140A (en) Pattern formation method of semiconductor device
KR980005531A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR940002956A (en) Metal wiring formation method
KR970077456A (en) Method of forming a contact hole in a semiconductor device
KR970077096A (en) Method of manufacturing semiconductor device
KR980005529A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR960002569A (en) How to Form Metal Wiring Alignment Keys
KR970072096A (en) Method for forming bonding pads of semiconductor devices
KR980005572A (en) Method for forming a metal layer pattern of a semiconductor element
KR970072308A (en) Field oxide film forming method of semiconductor device
KR980011762A (en) Method of manufacturing integrated circuit
KR970052239A (en) Via contact formation method of semiconductor device
KR960012638B1 (en) Mounting method of semiconducter wafer
KR970077232A (en) Method of forming a small contact hole in a semiconductor device
KR970072100A (en) A method of forming a multilayer metal wiring layer on a silicon substrate
KR970072319A (en) Method for forming interlayer insulating film of semiconductor device
KR970067646A (en) Method of forming a contact hole in a semiconductor device

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000