KR970077366A - Method of manufacturing high-voltage transistor - Google Patents

Method of manufacturing high-voltage transistor Download PDF

Info

Publication number
KR970077366A
KR970077366A KR1019960014660A KR19960014660A KR970077366A KR 970077366 A KR970077366 A KR 970077366A KR 1019960014660 A KR1019960014660 A KR 1019960014660A KR 19960014660 A KR19960014660 A KR 19960014660A KR 970077366 A KR970077366 A KR 970077366A
Authority
KR
South Korea
Prior art keywords
region
forming
source
predetermined
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019960014660A
Other languages
Korean (ko)
Other versions
KR100192183B1 (en
Inventor
송택근
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960014660A priority Critical patent/KR100192183B1/en
Publication of KR970077366A publication Critical patent/KR970077366A/en
Application granted granted Critical
Publication of KR100192183B1 publication Critical patent/KR100192183B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 제조방법에 있어서, 트랜지스터의 채널영역에 소오스/드레인 드립트(drift) 영역과 같은 타입의 채널 드립트 영역을 형성함으로써 펀치 쓰루 현상을 방지함과 더불어, 트랜지스터 구동에 따른 동작 저항을 감소시킬 수 있는 고전압 트랜지스터의 제조방법에 관한 것으로, 반도체 기판상에 소정의 웰을 형성한 후, 상기 웰 영역에 소정의 소오스/드레인 드립트영역을 형성한 다음, 웰 영역 상부에 필드 산화막 및 게이트 절연막을 형성하고 상기 게이트 절연막 상부에 소정의 게이트 전극을 형성한 후, 상기 소오스/드레인 드립트 영역의 소정 부분에 소오스/드레인의 고농도 주입 영역을 형성하여 접합영역을 구축하는 고전압 트랜지스터의 제조방법에 있어서, 상기 소오스/드레인 드립트 영역의 형성시 상기 게이트 전극 하부에 있는 상기 반도체 기판 표면에 소정의 채널 드립트 영역을 형성하는 것을 특징으로 한다.The present invention relates to a method of manufacturing a semiconductor device, in which a punch-through phenomenon is prevented by forming a channel drip region of the same type as a source / drain drift region in a channel region of a transistor, A method for fabricating a high voltage transistor, the method comprising: forming a predetermined well on a semiconductor substrate; forming a predetermined source / drain region in the well region; And forming a junction region by forming a gate insulating film, forming a predetermined gate electrode on the gate insulating film, and forming a high concentration injection region of a source / drain in a predetermined portion of the source / drain region, The method of claim 1, further comprising forming a source / drain region Is characterized in that a predetermined channel drip region is formed on the surface of the semiconductor substrate.

Description

고전압 트랜지스터의 제조방법Method of manufacturing high-voltage transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2a도 내지 제2f도는 본 발명의 일 실시예에 따른 고전압 트랜지스터의 제조방법을 나타낸 공정 단면도.FIGS. 2a through 2f are process cross-sectional views illustrating a method of manufacturing a high-voltage transistor according to an embodiment of the present invention.

Claims (2)

반도체 기판상에 소정의 웰을 형성한 후, 상기 웰 영역에 소정의 소오스/드레인 드립트 영역을 형성한 다음, 웰 영역 상부에 필드 산화막 및 게이트 절연막을 형성하고 상기 게이트 절연막 상부에 소정의 게이트 전극을 형성한 후, 상기 소오스/드레인 드립트 영역의 소정 부분에 소오스/드레인 고농도 주입 영역을 형성하여 접합영역을 구축하는 고전압 트랜지스터의 제조방법에 있어서, 상기 소오스/드레인 드립트 영역의 형성시 상기 게이트 전극 하부에 있는 상기 반도체 기판 표면에 소정의 채널 드립트 영역을 형성하는 것을 특징으로 하는 고전압 트랜지스터의 제조방법.A predetermined source / drain region is formed in the well region, a field oxide film and a gate insulating film are formed on the well region, a predetermined gate electrode / drain region is formed on the gate insulating film, Drain region, and forming a junction region by forming a source / drain high concentration implant region in a predetermined portion of the source / drain region, the method comprising the steps of: forming a source / Wherein a predetermined channel drip region is formed on the surface of the semiconductor substrate at the bottom of the electrode. 제1항에 있어서, 상기 채널 드립트 영역은 상기 소오스/드레인 드립트 영역과 동일한 불순물 농도를 갖는 것을 특징으로 하는 고전압 트랜지스터 제조방법.The method of claim 1, wherein the channel drip region has the same impurity concentration as the source / drain region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960014660A 1996-05-06 1996-05-06 Manufacturing method of high voltage transistor Expired - Lifetime KR100192183B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960014660A KR100192183B1 (en) 1996-05-06 1996-05-06 Manufacturing method of high voltage transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960014660A KR100192183B1 (en) 1996-05-06 1996-05-06 Manufacturing method of high voltage transistor

Publications (2)

Publication Number Publication Date
KR970077366A true KR970077366A (en) 1997-12-12
KR100192183B1 KR100192183B1 (en) 1999-06-15

Family

ID=19457800

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960014660A Expired - Lifetime KR100192183B1 (en) 1996-05-06 1996-05-06 Manufacturing method of high voltage transistor

Country Status (1)

Country Link
KR (1) KR100192183B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101175231B1 (en) 2005-04-11 2012-08-21 매그나칩 반도체 유한회사 A semiconductor device and method for manufacturing the same
KR100770539B1 (en) 2006-08-11 2007-10-25 동부일렉트로닉스 주식회사 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
KR100192183B1 (en) 1999-06-15

Similar Documents

Publication Publication Date Title
KR930006977A (en) Semiconductor device and manufacturing method thereof
KR970072205A (en) s. Five. SOI-type transistor and manufacturing method thereof
KR970004066A (en) Heterostructure insulated gate field effect transistor and method for forming the same
JPS55148464A (en) Mos semiconductor device and its manufacture
KR960012539A (en) Semiconductor device and manufacturing method
KR970017963A (en) Semiconductor device and manufacturing method thereof
KR930005257A (en) Thin film field effect element and its manufacturing method
KR950021772A (en) Method of manufacturing integrated circuit having at least one MOS transistor
KR890013796A (en) Semiconductor device and manufacturing method
KR960036128A (en) Silicon carbide metal oxide semiconductor field effect transistor
KR970077399A (en) Semiconductor component with compensation injection and manufacturing method thereof
EP0239250A3 (en) Short channel mos transistor
KR950021537A (en) High Voltage Transistors for Sub-micron CMOS Process
KR970063780A (en) Transistor manufacturing method
KR970077366A (en) Method of manufacturing high-voltage transistor
KR900015311A (en) Semiconductor device and manufacturing method
KR940016937A (en) Morse transistor having a non-uniform doped channel using a trench structure and a method of manufacturing the same
KR970004074A (en) Insulated gate field effect transistor and its manufacturing method
KR970008621A (en) Method for manufacturing semiconductor integrated circuit device
KR970072477A (en) Morse transistor structure and manufacturing method
KR980005882A (en) MOS transistor and its manufacturing method
KR980005844A (en) Method of manufacturing semiconductor device
KR980005881A (en) Method of manufacturing semiconductor device
KR960019608A (en) Transistor manufacturing method of semiconductor device
KR970063782A (en) High-voltage transistor

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19960506

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19960506

Comment text: Request for Examination of Application

PG1501 Laying open of application
E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19981030

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19990128

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19990129

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20011214

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20021223

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20031219

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20041230

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20051223

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20061215

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20080102

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20090102

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20091217

Start annual number: 12

End annual number: 12

PR1001 Payment of annual fee

Payment date: 20101217

Start annual number: 13

End annual number: 13

PR1001 Payment of annual fee

Payment date: 20111222

Start annual number: 14

End annual number: 14

PR1001 Payment of annual fee

Payment date: 20121210

Start annual number: 15

End annual number: 15

FPAY Annual fee payment

Payment date: 20131217

Year of fee payment: 16

PR1001 Payment of annual fee

Payment date: 20131217

Start annual number: 16

End annual number: 16

FPAY Annual fee payment

Payment date: 20141222

Year of fee payment: 17

PR1001 Payment of annual fee

Payment date: 20141222

Start annual number: 17

End annual number: 17

FPAY Annual fee payment

Payment date: 20151217

Year of fee payment: 18

PR1001 Payment of annual fee

Payment date: 20151217

Start annual number: 18

End annual number: 18

EXPY Expiration of term
PC1801 Expiration of term