KR970077385A - 반도체 디바이스 및 반도체 디바이스용 패키지 - Google Patents

반도체 디바이스 및 반도체 디바이스용 패키지 Download PDF

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KR970077385A
KR970077385A KR1019970022079A KR19970022079A KR970077385A KR 970077385 A KR970077385 A KR 970077385A KR 1019970022079 A KR1019970022079 A KR 1019970022079A KR 19970022079 A KR19970022079 A KR 19970022079A KR 970077385 A KR970077385 A KR 970077385A
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semiconductor device
device package
base substrate
metal base
wiring pattern
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카츠노부 스즈키
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가네꼬 히사시
닛폰 덴키 가부시키가이샤
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    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
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    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/00—Package configurations
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    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
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Abstract

검사가 용이하고, 신로도가 향상되었고, 양호한 열적 특성을 갖는 반도체 패키지 및 반도체 디바이스가 제공되고 그 제조 방법이 제공된다. 유기 재료로 만들어진 절연체 및 금속박에 의해 형성된 배선 패턴이 금속 베이스 기판의 상부 위에 형성되고, 이에 의해 적층 구조를 형성한다. 금속 베이스 기판은 복수의 전기적 절연 연속 검사 단자를 갖는다. 금속 베이스 기판, 연속 검사 단자, 및 배선 패턴은 소정의 위치에서 절연체를 가로지르는 비아 홀에 의해 접속된다. 절연체 및 배선 패턴은 반도체 칩이 형성되는 소정의 위치에서 제거된다. 노출된 금속 베이스 기판은 소정의 깊이를 갖는 공동처럼 형성된다.

Description

반도체 디바이스 및 반도체 디바이스용 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1a도 및 제1b도는 각각 본 발명에 따른 제1실시예의 구조를 도시하는 횡단면도 및 사시도.

Claims (16)

  1. 미리 정해져 디자인된 배선 패턴으로 형성되어 구성되는 금속 베이스 기판과, 절연층과, 금속막층으로 이루어진 다적층 기판을 포함하고, 적어도 하나의 연속 검사 단자가 상기 다적층 기판의 상기 금속 베이스 기판의 일부 및 상기 배선 패턴의 일부의 반대측에 제공되고, 상기 연속 검사 단자는 상기 금속 베이스 기판으로부터 격리되고 또한 상기 금속 베이스 기판과 전기적으로 절연되며, 적어도 하나의 솔더볼이 상기 금속 베이스 기판에 반대쪽인 배면측의 표면인 상기 배선 패턴의 표면 위 및 상기 연속 검사 단자가 제공되는 지점과 반대쪽인 상기 배선 패턴 상의 소정의 지점에 제공되는 것을 특징으로 하는 반도체 디바이스 패키지.
  2. 제1항에 있어서, 상기 연속 검사 단자는 상기 금속 베이스 기판에 대해 신축성 있도록 상기 배선 패턴에 따라 형성되는 것을 특징으로 하는 반도체 디바이스 패키지.
  3. 제1항에 있어서, 상기 연속 검사 단자 및 상기 배선 패턴의 소정 부분은 상기 절연층에 제공된 비아 홀(via hole)을 통해 서로 접속되는 것을 특징으로 하는 반도체 디바이스 패키지.
  4. 제1항에 있어서, 적어도 상기 배선 패턴의 일부는 적당한 접속 수단을 통해 상기 금속 베이스 기판의 표면상에 설치되는 상기 반도체 칩 상에 형성된 적어도 하나의 접속 패드와 접속되는 것을 특징으로 하는 반도체 디바이스 패키지.
  5. 제4항에 있어서, 상기 반도체 칩, 상기 접속 수단, 및 상기 배선 패턴의 일부는 소정의 봉합 재료로 봉합되는 것을 특징으로 하는 반도체 디바이스 패키지.
  6. 제1항에 있어서, 상기 반도체칩을 설치하는 부분은 평평하고 상기 금속 베이스 기판과 동일한 기판 상에 있는 것을 특징으로 하는 반도체 디바이스 패키지.
  7. 제1항에 있어서, 상기 반도체 칩을 설치하는 부분을 함몰부가 형성되어 있고, 상기 반도체 칩은 상기 함몰부 내에 설치되는 것을 특징으로 하는 반도체 디바이스 패키지.
  8. 제1항에 있어서, 설치된 반도체 칩 및 상기 패키지간의 접속은 배선 접합방법, 솔더볼이 상기 반도체칩 상에 형성되는 솔더볼 방법, 및 플립칩 방법에서 선택된 소정의 방법에 의해 이루어지는 것을 특징으로 하는 반도체 디바이스 패키지.
  9. 제1항에 있어서, 상기 반도체 칩 설치 부분 및 상기 반도체 칩은 저융융점 금속, 또는 유기 금속을 함유하는 수지를 이용함으로써 접속되고 설치되는 것을 특징으로 하는 반도체 디바이스 패키지.
  10. 제1항에 있어서, 상기 봉합 재료는 유기 수지인 것을 특징으로 하는 반도체 디바이스 패키지.
  11. 제1항에 있어서, 상기 금속 베이스 기판 및 금속박층은 구리 또는 알루미늄으로 만들어지는 것을 특징으로 하는 반도체 디바이스 패키지.
  12. 제1항에 있어서, 반도체 칩이 설치되는 상기 칩 설치 부분 위에는 절연층 및 금속막층이 제공되지 않는 것을 특징으로 하는 반도체 디바이스 패키지.
  13. 제1항에 있어서, 설치 재료는 상기 칩 설치 부분 상에 제공되는 것을 특징으로 하는 반도체 디바이스 패키지.
  14. 제1항에서 청구된 반도체 디바이스 패키지를 다수 포함하고, 각각의 상기 반도체 디바이스 패키지들은 서로 층층이 적층되므로 한 반도체 디바이스 패키지의 연속 검사 단자는 상기 반도체 디바이스 패키지 위에 적층되어 있는 또다른 반도체 디바이스 패키지 위에 형성된 솔더볼과 상호 접속되는 것을 특징으로 하는 반도체 디바이스.
  15. 세층으로된 적층 기판을 포함하고, 상기 기판은 금속 베이스 기판, 절연층, 및 금속막층을 포함하고, 배선 패턴은 상기 금속막층 위에 형성되고, 상기 금속 베이스 기판의 일부분 위에 반도체 칩이 설치되는 패키지 제조 방법에 있어서, 필링(peeling) 발생 방지 수단이 형성될 부분 주변의 상기 금속 베이스 기판의 일부를 제거하여 상기 금속 베이스 기판에 상기 필링 발생 방지 수단을 형성시켜 상기 절연층을 노출시키고 상기 금속 베이스 기판으로부터 상기 필링 발생 방지수단을 전기적으로 분리하는 단계와, 상기 절연층 안쪽에 형성된 비아 홀을 통해서 상기 배선 패턴의 일부와 상기 필링 방지 수단을 접속하는 단계와, 상기 필링 발생 방지 수단이 접속되는 상기 배선 패턴의 일부분 위에 솔더볼을 형성하는 단계를 포함하는 것을 특징으로 하는 패키지 제조 방법.
  16. 반도체 디바이스 제조 방법에 있어서, 제1항에 의해 한정되는 복수의 반도체 디바이스 패키지를 준비하는 단계와, 각각의 상기 반도체 디바이스 패키지들은 서로 층층이 적층하는 단계와, 한 반도체 디바이스 패키지 위에 제공된 연속 검사 단자를 상기 반도체 디바이스 패키지 위에 적층되는 또다른 반도체 디바이스 패키지상에 제공된 솔더볼과 접속시켜 두 반도체 디바이스 패키지들 간에 전기적 경로를 형성하는 단계를 포함하는 것을 특징으로 하는 패키지 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970022079A 1996-05-30 1997-05-30 반도체 디바이스 및 반도체 디바이스용 패키지 Expired - Fee Related KR100252731B1 (ko)

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JP8137224A JP2755252B2 (ja) 1996-05-30 1996-05-30 半導体装置用パッケージ及び半導体装置
JP96-137224 1996-05-30

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KR970077385A true KR970077385A (ko) 1997-12-12
KR100252731B1 KR100252731B1 (ko) 2000-04-15

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