KR970077488A - 반도체 장치의 트렌치 소자 분리 방법 - Google Patents

반도체 장치의 트렌치 소자 분리 방법 Download PDF

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Publication number
KR970077488A
KR970077488A KR1019960017207A KR19960017207A KR970077488A KR 970077488 A KR970077488 A KR 970077488A KR 1019960017207 A KR1019960017207 A KR 1019960017207A KR 19960017207 A KR19960017207 A KR 19960017207A KR 970077488 A KR970077488 A KR 970077488A
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Prior art keywords
insulating material
trench
layer pattern
semiconductor device
mask layer
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KR1019960017207A
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KR0183860B1 (ko
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박태서
박문한
신유균
이한신
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김광호
삼성전자 주식회사
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Priority to KR1019960017207A priority Critical patent/KR0183860B1/ko
Priority to US08/729,453 priority patent/US5858858A/en
Priority to JP8287944A priority patent/JPH09321132A/ja
Publication of KR970077488A publication Critical patent/KR970077488A/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

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Abstract

본 발명은 반도체 장치의 트렌치 소자 분리 방법에 관한 것으로, 본 발명에서는 반도체 장치의 소자 분리 공정에 있어서 트렌치를 매립하기 위한 절연 물질을 1000∼1400℃의 온도에서 30분∼8시간 동안 어닐링하여 치밀화 한다. 본 발명에 의하면, 트렌치 매립 물질의 치밀화 효율이 향상되어 험프 현상이나 역 협폭 효과를 방지할 수 있다.

Description

반도체 장치의 트렌치 소자 분리 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 내지 제8도는 본 발명의 바람직한 실시예에 따른 반도체 장치의 트렌치 소자 분리 방법을 설명하기 위한 단면도들이다.

Claims (3)

  1. 반도체 기판 상에 패드층, 마스크층 및 버퍼층을 차례로 형성하는 단계와, 상기 버퍼층, 마스크층 및패드층을 패터닝하여 활성 영역을 정의 하는 버퍼층 패턴, 마스크층 패턴 및 패드층 패턴을 형성하는 단계와,상기 버퍼층 패턴을 제거하는 단계와, 상기 마스크층 패턴을 마스크로 하여 상기 반도체 기판을 소정의 깊이로식각하여 트렌치를 형성하는 단계와, 상기 트렌치를 내벽에 산화막을 형성하는 단계와, 상기 트렌치를 매립하기 위한 절연 물질을 증착하는 단계와, 상기 절연 물질을 1000~1400℃의 온도에서 30분~8시간 동안 어닐링하여 치밀화하는 단계와, 상기 마스크층 패턴이 노출될 때까지 상기 절연 물질 및 산화막을 CMP(ChemicalMechanical Polishing) 공정을 이용하여 평탄화하는 단계와, 상기 마스크층 패턴 및 패드층 패턴을 차례로제거하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 트렌치 소자 분리 방법.
  2. 제1항에 있어서, 상기 절연 물질은 CVD(Chemical Vapor Deposition)에 의해 증착된 산화막으로 형성하는 것을 특징으로 하는 반도체 장치의 트렌치 소자 분리 방법.
  3. 제1항에 있어서, 상기 절연 물질을 어닐링하는 단계는 불활성 가스 분위기에서 행하는 것을 특징으로 하는 반도체 장치의 트렌치 소자 분리 방법
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960017207A 1996-05-21 1996-05-21 반도체 장치의 트렌치 소자 분리 방법 Expired - Lifetime KR0183860B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019960017207A KR0183860B1 (ko) 1996-05-21 1996-05-21 반도체 장치의 트렌치 소자 분리 방법
US08/729,453 US5858858A (en) 1996-05-21 1996-10-11 Annealing methods for forming isolation trenches
JP8287944A JPH09321132A (ja) 1996-05-21 1996-10-30 半導体装置のトレンチ素子分離方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960017207A KR0183860B1 (ko) 1996-05-21 1996-05-21 반도체 장치의 트렌치 소자 분리 방법

Publications (2)

Publication Number Publication Date
KR970077488A true KR970077488A (ko) 1997-12-12
KR0183860B1 KR0183860B1 (ko) 1999-04-15

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US (1) US5858858A (ko)
JP (1) JPH09321132A (ko)
KR (1) KR0183860B1 (ko)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980015598A (ko) * 1996-08-23 1998-05-25 김주용 반도체 소자의 소자분리막 형성방법
KR20010046070A (ko) * 1999-11-10 2001-06-05 박종섭 반도체소자의 격리영역 형성방법
KR100334245B1 (ko) * 1998-03-24 2002-05-02 마찌다 가쯔히꼬 소자분리영역의 형성 방법
KR100338771B1 (ko) * 1999-11-12 2002-05-30 윤종용 수소 어닐링 단계를 포함하는 공정이 간단한 트렌치소자분리방법

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US5818438A (en) * 1995-04-25 1998-10-06 Bellsouth Corporation System and method for providing television services
US6097076A (en) * 1997-03-25 2000-08-01 Micron Technology, Inc. Self-aligned isolation trench
US6090683A (en) 1997-06-16 2000-07-18 Micron Technology, Inc. Method of etching thermally grown oxide substantially selectively relative to deposited oxide
US6165853A (en) * 1997-06-16 2000-12-26 Micron Technology, Inc. Trench isolation method
US5976947A (en) * 1997-08-18 1999-11-02 Micron Technology, Inc. Method for forming dielectric within a recess
US6001706A (en) * 1997-12-08 1999-12-14 Chartered Semiconductor Manufacturing, Ltd. Method for making improved shallow trench isolation for semiconductor integrated circuits
US6124183A (en) * 1997-12-18 2000-09-26 Advanced Micro Devices, Inc. Shallow trench isolation formation with simplified reverse planarization mask
JPH11274287A (ja) 1998-03-24 1999-10-08 Sharp Corp 素子分離領域の形成方法
KR100468712B1 (ko) * 1998-06-19 2005-04-06 삼성전자주식회사 열산화 공정을 포함하지 않는 반도체장치의 트렌치 소자분리방법
KR100268419B1 (ko) * 1998-08-14 2000-10-16 윤종용 고집적 반도체 메모리 장치 및 그의 제조 방법
KR100275600B1 (ko) * 1998-08-27 2000-12-15 한신혁 반도체 소자의 트렌치 형성 방법
US6093652A (en) * 1998-09-03 2000-07-25 Micron Technology, Inc. Methods of forming insulative plugs, and oxide plug forming methods
US5960299A (en) * 1998-10-28 1999-09-28 United Microelectronics Corp. Method of fabricating a shallow-trench isolation structure in integrated circuit
TW406353B (en) * 1999-04-08 2000-09-21 Mosel Vitelic Inc Method of forming a concave oxidized structure at the trench bottom
US6350662B1 (en) 1999-07-19 2002-02-26 Taiwan Semiconductor Manufacturing Company Method to reduce defects in shallow trench isolations by post liner anneal
JP3439388B2 (ja) * 1999-07-27 2003-08-25 日本電気株式会社 半導体装置の製造方法
US6277697B1 (en) * 1999-11-12 2001-08-21 United Microelectronics Corp. Method to reduce inverse-narrow-width effect
JP3344397B2 (ja) * 2000-01-21 2002-11-11 日本電気株式会社 半導体装置の製造方法
US6271100B1 (en) 2000-02-24 2001-08-07 International Business Machines Corporation Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield
US6817903B1 (en) 2000-08-09 2004-11-16 Cypress Semiconductor Corporation Process for reducing leakage in an integrated circuit with shallow trench isolated active areas
US20020068415A1 (en) * 2000-12-01 2002-06-06 Hua-Chou Tseng Method of fabricating a shallow trench isolation structure
JP4018596B2 (ja) 2002-10-02 2007-12-05 株式会社東芝 半導体装置の製造方法
KR100621621B1 (ko) 2003-12-19 2006-09-13 삼성전자주식회사 자기 정렬된 게이트 도전막을 구비하는 비휘발성 메모리장치 및 그 제조 방법
KR100724196B1 (ko) * 2005-12-28 2007-05-31 동부일렉트로닉스 주식회사 반도체 소자의 ｓｔｉ 갭필 산화막 제조방법
US20070249129A1 (en) * 2006-04-21 2007-10-25 Freescale Semiconductor, Inc. STI stressor integration for minimal phosphoric exposure and divot-free topography

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US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
US5492858A (en) * 1994-04-20 1996-02-20 Digital Equipment Corporation Shallow trench isolation process for high aspect ratio trenches
US5445989A (en) * 1994-08-23 1995-08-29 United Microelectronics Corp. Method of forming device isolation regions

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980015598A (ko) * 1996-08-23 1998-05-25 김주용 반도체 소자의 소자분리막 형성방법
KR100334245B1 (ko) * 1998-03-24 2002-05-02 마찌다 가쯔히꼬 소자분리영역의 형성 방법
KR20010046070A (ko) * 1999-11-10 2001-06-05 박종섭 반도체소자의 격리영역 형성방법
KR100338771B1 (ko) * 1999-11-12 2002-05-30 윤종용 수소 어닐링 단계를 포함하는 공정이 간단한 트렌치소자분리방법

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Publication number Publication date
JPH09321132A (ja) 1997-12-12
KR0183860B1 (ko) 1999-04-15
US5858858A (en) 1999-01-12

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