KR970077491A - Device separation membrane manufacturing method - Google Patents

Device separation membrane manufacturing method Download PDF

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Publication number
KR970077491A
KR970077491A KR1019960017365A KR19960017365A KR970077491A KR 970077491 A KR970077491 A KR 970077491A KR 1019960017365 A KR1019960017365 A KR 1019960017365A KR 19960017365 A KR19960017365 A KR 19960017365A KR 970077491 A KR970077491 A KR 970077491A
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KR
South Korea
Prior art keywords
spacer
silicon substrate
nitride
oxide film
film
Prior art date
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Withdrawn
Application number
KR1019960017365A
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Korean (ko)
Inventor
김숭준
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960017365A priority Critical patent/KR970077491A/en
Publication of KR970077491A publication Critical patent/KR970077491A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 소자분리마스크용 질화막 패턴의 측벽에 형성되는 질화막 스페이서의 저부면이 실리콘 기판과 직접 접촉되는 면적을 최소화하기 위하여 질화막 스페이서의 저부면에 산화막 스페이서를 형성한다. 그로인하여 질화막 스페이서가 실리콘기판에 직접 접촉되는 영역이 최소화되어 질화막 스페이서에 의해 실리콘기판이 받는 스트레스가 감소되고 그 결과 실리콘 기판내에 발생되는 결함을 최소화 할 수 있는 기술이다.The present invention relates to a method of manufacturing an element isolation film for a semiconductor device, in which an oxide spacer is formed on a bottom surface of a nitride spacer so as to minimize an area where a bottom surface of a nitride spacer formed on a sidewall of a nitride- . Thereby minimizing the area where the nitride film spacer directly contacts the silicon substrate, thereby reducing the stress of the silicon substrate due to the nitride film spacer, thereby minimizing defects occurring in the silicon substrate.

Description

소자분리막 제조방법Device separation membrane manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제6도 내지 제12도는 본 발명에 의해 실리콘기판에 소자분리막을 제조하는 과정을 도시한 단면도.6 to 12 are cross-sectional views illustrating a process of manufacturing an element isolation film on a silicon substrate according to the present invention.

Claims (2)

실리콘기판 상부에 패드산화막과 질화막을 적층하고, 소자분리막 마스크를 이용한 식각공정으로 소자분리막이 형성될 지역의 질화막과 패드산화막을 식각하여 질화막과 패드산화막의 패턴을 형성하는 동시에 실리콘기판의 일정두께를 식각하여 홈을 형성하는 단계와, 노출된 실리콘기판을 산화시켜 산화막을 형성하는 단계와, 상기 산화막을 이방성 식각하여 상기 홈의 측벽에 산화막 스페이서를 형성하는 단계와, 상기 질화막 패턴과 상기 산화막 스페이서 측벽에 질화막 스페이서를 형성하는 단계와, 노출된 실리콘 기판을 산화시켜 소자분리산화막을 형성하는 단계를 포함하는 소자분리막 제조방법.A pad oxide film and a nitride film are stacked on a silicon substrate, and a nitride film and a pad oxide film are etched by an etching process using an isolation film mask to form a pattern of a nitride film and a pad oxide film, Forming an oxide film on the sidewall of the groove by anisotropically etching the oxide film; and forming an oxide film spacer on the sidewall of the groove, Forming a nitride film spacer on the exposed silicon substrate; and oxidizing the exposed silicon substrate to form a device isolation oxide film. 제1항에 있어서, 상기 질화막 스페이서를 형성한 다음, 노출된 실리콘 기판을 식각하여 홈을 형성한 후,소자분리산화막을 형성하는 것을 특징으로 하는 소자분리막 제조방법.The device isolation film manufacturing method according to claim 1, wherein after the nitride film spacer is formed, the exposed silicon substrate is etched to form a groove, and then a device isolation oxide film is formed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960017365A 1996-05-22 1996-05-22 Device separation membrane manufacturing method Withdrawn KR970077491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960017365A KR970077491A (en) 1996-05-22 1996-05-22 Device separation membrane manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960017365A KR970077491A (en) 1996-05-22 1996-05-22 Device separation membrane manufacturing method

Publications (1)

Publication Number Publication Date
KR970077491A true KR970077491A (en) 1997-12-12

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ID=66219687

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960017365A Withdrawn KR970077491A (en) 1996-05-22 1996-05-22 Device separation membrane manufacturing method

Country Status (1)

Country Link
KR (1) KR970077491A (en)

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