KR970077968A - DC offset elimination circuit - Google Patents

DC offset elimination circuit Download PDF

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Publication number
KR970077968A
KR970077968A KR1019960015604A KR19960015604A KR970077968A KR 970077968 A KR970077968 A KR 970077968A KR 1019960015604 A KR1019960015604 A KR 1019960015604A KR 19960015604 A KR19960015604 A KR 19960015604A KR 970077968 A KR970077968 A KR 970077968A
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KR
South Korea
Prior art keywords
signal source
amplifier
resistor
input terminal
offset
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Withdrawn
Application number
KR1019960015604A
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Korean (ko)
Inventor
박종규
최경선
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김광호
삼성전자 주식회사
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Priority to KR1019960015604A priority Critical patent/KR970077968A/en
Publication of KR970077968A publication Critical patent/KR970077968A/en
Withdrawn legal-status Critical Current

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Abstract

본 발명은 DC 오프셋 제거회로에 관한 것으로서, 특히 OP 앰프를 이용한 DC 오프셋 제거회로에 관한 것이다.The present invention relates to a DC offset removing circuit, and more particularly, to a DC offset removing circuit using an OP amplifier.

본 발명에 따른 DC 오프셋 제거회로는 제 1 OP 앰프의 부입력단자에 제 1 저항과 DC 성분이 포함된 신호원을 직렬 접속하고 상기 부입력단자와 상기 제 1 OP 앰프의 출력단자 사이에 제 2 저항을 접속하고 상기 제 1 OP 앰프의 정입력단자에 상기 신호원의 DC 성분의 전압원과 제 3 저항을 직렬 접속하고 상기 정입력단자와 접지 사이를 제 4 저항으로 연결하는 차동 증폭부 ; 및 상기 차동증폭부의 출력을 유입하여 원래의 위상으로 반전시키고 증폭도를 제어하여 상기 신호원의 AC 레벨과 동일하게 출력시키는 인버팅 증폭부를 포함함을 특징으로 한다. 상술한 바와 같이 본 발명에 따른 오프셋 제거회로는 종래의 카플링 캐패시터에 의한 세팅 타임을 없애고 AC 신호원의 주파수 변화에 따른 레벨이나 위상 변동을 방지한다.A DC offset canceling circuit according to the present invention is characterized in that a signal source including a first resistor and a DC component is connected in series to a negative input terminal of a first operational amplifier and a second positive input is connected between the negative input terminal and an output terminal of the first operational amplifier A differential amplifying unit connecting a resistor and connecting a voltage source of a DC component of the signal source and a third resistor in series to a positive input terminal of the first OP amplifier and connecting a fourth resistor between the positive input terminal and the ground; And an inverting amplifier for inverting the output of the differential amplifier to an original phase and controlling the amplification to output the same as the AC level of the signal source. As described above, the offset eliminating circuit according to the present invention eliminates the setting time by the conventional coupling capacitor and prevents the level or phase fluctuation according to the frequency change of the AC signal source.

Description

디씨(DC) 오프셋 제거회로DC offset elimination circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제 1 도는 본 발명에 따른 DC 오프셋을 제거하는 일 실시예의 회로도이다. 제 2 도는 본 발명에 따른 DC 오프셋을 제거하는 다른 실시예의 회로도이다.FIG. 1 is a circuit diagram of one embodiment for removing a DC offset in accordance with the present invention. 2 is a circuit diagram of another embodiment for eliminating the DC offset according to the present invention.

Claims (3)

DC 오프셋 제거회로에 있어서, 제 1 OP 앰프의 부입력단자에 제 1 저항과 DC 성분이 포함된 신호원을 직렬 접속하고 상기 부입력단자와 상기 제 1 OP 앰프의 출력단자 사이에 제 2 저항을 접속하고 상기 제 1 OP 앰프의 정입력단자에 상기 신호원의 DC 성분의 전압원과 제 3 저항을 직렬 접속하고 상기 정입력단자와 접지 사이를 제 4 저항으로 연결하는 차동 증폭부 ; 및 상기 차동증폭부의 출력을 유입하여 원래의 위상으로 반전시키고 증폭도를 제어하여 상기 신호원의 AC 레벨과 동일하게 출력시키는 인버팅 증폭부를 포함함을 특징으로 하는 DC 오프셋 제거회로.A DC offset removing circuit comprising: a first resistor connected in series with a first resistor and a signal source including a DC component to a negative input terminal of the first operational amplifier; and a second resistor between the negative input terminal and the output terminal of the first operational amplifier A differential amplification unit connected to a positive input terminal of the first OP amplifier in series between a voltage source and a third resistor of a DC component of the signal source and connecting a fourth resistor between the positive input terminal and the ground; And an inverting amplifier for inverting the output of the differential amplifier to an original phase and controlling the amplification to output the same as the AC level of the signal source. 제 1 항에 있어서, 상기 제 1 저항과 상기 제 2 저항비는 상기 제 3 저항과 상기 제 4 저항비와 동일함을 특징으로 하는 DC 오프셋 제거회로.2. The DC offset removal circuit of claim 1, wherein the first resistance and the second resistance ratio are the same as the third resistance and the fourth resistance ratio. 서로 반전되고 DC 오프셋을 갖는 신호들을 유입하여 DC 오프셋을 제거하는 회로에 있어서, 제 1 OP 앰프의 부입력단자에 제 1 저항과 DC 성분이 포함된 제 1 신호원을 직렬 접속하고 상기 부입력단자와 상기 제 1 OP 앰프의 출력단자 사이에 제 2 저항을 접속하고 상기 제 1 OP 앰프의 정입력단자에 상기 제 1 신호원의 DC 성분의 전압원과 제 3 저항을 직렬 접속하고 상기 정입력단자와 접지 사이를 제 4 저항으로 연결하는 차동 증폭부 ; 상기 제 1 차동 증폭부의 동일한 구조를 갖으며 상기 제 1 신호원과 위상이 반전된 제 2 신호원을 제 2 OP 앰프의 부입력단자측에 접속되고 상기 제 2 신호원의 오프셋 신호를 상기 제 2 OP 앰프의 정입력단자측에 접속하는 제 2 차동 증폭부 ; 및 상기 제 1 차동증폭부와 제 2 차동 증폭부의 출력을 유입하여 상기 제 1 신호원과 제 2 신호원의 반전 신호의 차를 증폭시키는 제 3 차동 증폭부를 포함함을 특징으로 하는 DC 오프셋 제거회로.A circuit for inverting each other and for inputting a signal having a DC offset to remove a DC offset, comprising: a first signal source including a first resistor and a DC component connected in series to a negative input terminal of a first operational amplifier, And a third resistor connected in series between the voltage source of the DC component of the first signal source and the positive input terminal of the first OP amplifier, A differential amplifying part connecting a ground to a fourth resistor; A second signal source having the same structure as that of the first differential amplifier and inverted in phase with the first signal source is connected to the negative input terminal side of the second OP amplifier and the offset signal of the second signal source is connected to the second A second differential amplifier connected to the positive input terminal of the operational amplifier; And a third differential amplifying unit for receiving the output of the first differential amplifying unit and the second differential amplifying unit and amplifying the difference between the inverted signals of the first signal source and the second signal source, . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960015604A 1996-05-11 1996-05-11 DC offset elimination circuit Withdrawn KR970077968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960015604A KR970077968A (en) 1996-05-11 1996-05-11 DC offset elimination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960015604A KR970077968A (en) 1996-05-11 1996-05-11 DC offset elimination circuit

Publications (1)

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KR970077968A true KR970077968A (en) 1997-12-12

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KR1019960015604A Withdrawn KR970077968A (en) 1996-05-11 1996-05-11 DC offset elimination circuit

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Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19960511

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid