MX2016003576A - Dispositivo de proceso de datos y metodo de proceso de datos. - Google Patents

Dispositivo de proceso de datos y metodo de proceso de datos.

Info

Publication number
MX2016003576A
MX2016003576A MX2016003576A MX2016003576A MX2016003576A MX 2016003576 A MX2016003576 A MX 2016003576A MX 2016003576 A MX2016003576 A MX 2016003576A MX 2016003576 A MX2016003576 A MX 2016003576A MX 2016003576 A MX2016003576 A MX 2016003576A
Authority
MX
Mexico
Prior art keywords
data processing
group
ldpc code
code
processing device
Prior art date
Application number
MX2016003576A
Other languages
English (en)
Inventor
Yuji Shinohara
Makiko Yamamoto
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of MX2016003576A publication Critical patent/MX2016003576A/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L2001/0092—Error control systems characterised by the topology of the transmission link
    • H04L2001/0093—Point-to-multipoint

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Algebra (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

La presente tecnología se refiere a un dispositivo de proceso de datos y a un método de proceso de datos que hace posible asegurar buena calidad de comunicación en una transmisión de datos que usa códigos de LDPC. En la intercalación en forma de grupos, un código de LDPC cuya longitud de código es 16200 bits y la tasa de códigos es de 10/15, 11/15, 12/15, o 13/15 se intercala en una unidad de grupo de 360 bits. En la desintercalación en forma de grupos, una secuencia del código de LDPC después de la intercalación en forma de grupos obtenida de los datos transmitidos de un dispositivo de transmisión a la secuencia original. La tecnología presente puede aplicarse, por ejemplo, para transmisión de datos o similares que usa los códigos de LDPC.
MX2016003576A 2013-09-26 2014-09-12 Dispositivo de proceso de datos y metodo de proceso de datos. MX2016003576A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013199087 2013-09-26
PCT/JP2014/074198 WO2015045899A1 (ja) 2013-09-26 2014-09-12 データ処理装置、及びデータ処理方法

Publications (1)

Publication Number Publication Date
MX2016003576A true MX2016003576A (es) 2016-06-02

Family

ID=52743041

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2016003576A MX2016003576A (es) 2013-09-26 2014-09-12 Dispositivo de proceso de datos y metodo de proceso de datos.

Country Status (8)

Country Link
US (1) US20160197625A1 (es)
EP (1) EP3051707A4 (es)
JP (1) JPWO2015045899A1 (es)
KR (1) KR20160061329A (es)
CN (1) CN105556854A (es)
CA (1) CA2924780A1 (es)
MX (1) MX2016003576A (es)
WO (1) WO2015045899A1 (es)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101929145B1 (ko) * 2013-06-12 2018-12-13 소니 주식회사 데이터 처리 장치, 및 데이터 처리 방법
WO2015041074A1 (ja) 2013-09-20 2015-03-26 ソニー株式会社 データ処理装置、及びデータ処理方法
CA2924027A1 (en) * 2013-09-24 2015-04-02 Sony Corporation Data processing device and data processing method
EP3148085B1 (en) * 2014-05-21 2021-02-24 Sony Corporation Bit interleaved coded modulation with a group-wise interleaver adapted to a rate 10/15 ldpc code of length 16200
CA2918520C (en) 2014-05-21 2023-10-10 Sony Corporation Data processing device and data processing method
US11070315B2 (en) * 2016-09-26 2021-07-20 Nokia Technologies Oy Error detection and channel coding of transport blocks
CN111602352B (zh) * 2018-01-15 2021-12-10 中兴通讯股份有限公司 用于促进无线通信网络中的多址接入的方法和计算设备

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US20020078416A1 (en) * 2000-12-01 2002-06-20 Hitachi, Ltd. Method of recording/reproducing digital data and apparatus for same
JP3875693B2 (ja) * 2004-03-24 2007-01-31 株式会社東芝 Ｌｐｃ符号を用いた符号化ビットのマッピング方法及び送信装置
US7543197B2 (en) * 2004-12-22 2009-06-02 Qualcomm Incorporated Pruned bit-reversal interleaver
DE602006011240D1 (de) * 2005-06-21 2010-02-04 Samsung Electronics Co Ltd Vorrichtung und Methode zum Übermitteln/Empfangen von Daten in einem Mehrantennenkommunikationssystem unter Verwendung eines strukturierten Low Density Parity Check (LDPC) Codes
NZ585421A (en) * 2007-11-26 2013-03-28 Sony Corp An apparatus for encoding using a low-density parity check code
CN101488819B (zh) * 2008-01-15 2013-02-27 华为技术有限公司 一种低密度奇偶校验码编码调制方法及装置
EP2134051A1 (en) * 2008-06-13 2009-12-16 THOMSON Licensing An adaptive QAM transmission scheme for improving performance on an AWGN channel
JP5630278B2 (ja) * 2010-12-28 2014-11-26 ソニー株式会社 データ処理装置、及びデータ処理方法
JP5664919B2 (ja) * 2011-06-15 2015-02-04 ソニー株式会社 データ処理装置、及び、データ処理方法
EP2560311A1 (en) * 2011-08-17 2013-02-20 Panasonic Corporation Cyclic-block permutations for spatial multiplexing with quasi-cyclic LDPC codes
KR20150005853A (ko) * 2013-07-05 2015-01-15 삼성전자주식회사 송신 장치 및 그의 신호 처리 방법
US9735809B2 (en) * 2013-09-26 2017-08-15 Samsung Electronics Co., Ltd. Transmitting apparatus and signal processing method thereof
CN105594130A (zh) * 2013-09-26 2016-05-18 索尼公司 数据处理装置和数据处理方法

Also Published As

Publication number Publication date
EP3051707A1 (en) 2016-08-03
EP3051707A4 (en) 2017-06-21
WO2015045899A1 (ja) 2015-04-02
JPWO2015045899A1 (ja) 2017-03-09
CA2924780A1 (en) 2015-04-02
US20160197625A1 (en) 2016-07-07
KR20160061329A (ko) 2016-05-31
CN105556854A (zh) 2016-05-04

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