MY118599A - Cache enabling architecture - Google Patents

Cache enabling architecture

Info

Publication number
MY118599A
MY118599A MYPI98004072A MYPI9804072A MY118599A MY 118599 A MY118599 A MY 118599A MY PI98004072 A MYPI98004072 A MY PI98004072A MY PI9804072 A MYPI9804072 A MY PI9804072A MY 118599 A MY118599 A MY 118599A
Authority
MY
Malaysia
Prior art keywords
writing
reading
cache
enabling architecture
caching
Prior art date
Application number
MYPI98004072A
Inventor
Lebegue Xavier
Schweer Rainer
Original Assignee
Thomson Brandt Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP97115527A external-priority patent/EP0901077A1/en
Application filed by Thomson Brandt Gmbh filed Critical Thomson Brandt Gmbh
Publication of MY118599A publication Critical patent/MY118599A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device
    • G06F3/0676—Magnetic disk device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0012—High speed serial bus, e.g. IEEE P1394

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A CACHE ENABLING ARCHITECTURE IN WHICH AN OPTICAL STORAGE READING AND/OR WRITING DEVICE (2), A CACHING PROCESSOR (5) AND A MASS WRITING AND READING DEVICE (3) ARE EACH CONNECTED TO A DATA BUS (1). THE OPTICAL STORAGE READING AND/OR WRITING DEVICE EXCHANGES INFORMATION DIRECTLY WITH THE CACHING PROCESSOR OVER THE DATA BUS. THE CACHING USES THE MASS WRITING AND READING DEVICE AS CACHE MEMORY.
MYPI98004072A 1997-09-08 1998-09-07 Cache enabling architecture MY118599A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5845297P 1997-09-08 1997-09-08
EP97115527A EP0901077A1 (en) 1997-09-08 1997-09-08 Cache enabling architecture

Publications (1)

Publication Number Publication Date
MY118599A true MY118599A (en) 2004-12-31

Family

ID=26145768

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI98004072A MY118599A (en) 1997-09-08 1998-09-07 Cache enabling architecture

Country Status (6)

Country Link
JP (1) JPH11167469A (en)
KR (1) KR100580933B1 (en)
CN (1) CN1119749C (en)
ID (1) ID20659A (en)
MY (1) MY118599A (en)
SG (1) SG70114A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101403982B (en) 2008-11-03 2011-07-20 华为技术有限公司 Task distribution method, system for multi-core processor

Also Published As

Publication number Publication date
KR19990029463A (en) 1999-04-26
HK1017115A1 (en) 1999-11-12
CN1211008A (en) 1999-03-17
CN1119749C (en) 2003-08-27
JPH11167469A (en) 1999-06-22
KR100580933B1 (en) 2006-10-24
ID20659A (en) 1999-02-11
SG70114A1 (en) 2000-01-25

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