MY162612A - Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus - Google Patents

Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus

Info

Publication number
MY162612A
MY162612A MYPI2012700814A MYPI2012700814A MY162612A MY 162612 A MY162612 A MY 162612A MY PI2012700814 A MYPI2012700814 A MY PI2012700814A MY PI2012700814 A MYPI2012700814 A MY PI2012700814A MY 162612 A MY162612 A MY 162612A
Authority
MY
Malaysia
Prior art keywords
access
local cache
local
access operation
shared
Prior art date
Application number
MYPI2012700814A
Inventor
Frederic Claude Marie Piry
Louis-Marie Vincent Mouton
Luca Scalabrino
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Publication of MY162612A publication Critical patent/MY162612A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

An apparatus and method are provided for handling access operations issued to local cache structures (310, 330, and 350) within a data processing apparatus. The data processing apparatus comprises a plurality of processing units (10, 40) each having a local cache structure (310) associated therewith. Shared access coordination circuitry (370) is also provided for coordinating the handling of shared access operations issued to any of the local cache structures (310, 330, 350). For a shared access operation, the access control circuitry associated with the local cache structure (310) to which that shared access operation is issued will perform a local access operation to that local cache structure (310), and in addition will issue a shared access signal to the shared access coordination circuitry (370). For a local access operation, the access control circuitry would normally perform a local access operation on the associated local cache structure (310), and not notify the shared access coordination circuitry (370). However, if an access operation extension value is set, then the access control circuitry treats such a local access operation as a shared access operation. Such an approach ensures correction operation even after an operating system (92) and/or an application program are migrated from one processing unit (10) to another.
MYPI2012700814A 2010-06-16 2011-05-11 Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus MY162612A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1010114.5A GB2481232A (en) 2010-06-16 2010-06-16 Cache for a multiprocessor system which can treat a local access operation as a shared access operation

Publications (1)

Publication Number Publication Date
MY162612A true MY162612A (en) 2017-06-30

Family

ID=42471761

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2012700814A MY162612A (en) 2010-06-16 2011-05-11 Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus

Country Status (10)

Country Link
US (1) US8706965B2 (en)
EP (1) EP2583182B1 (en)
JP (1) JP5543022B2 (en)
KR (1) KR101677900B1 (en)
CN (1) CN102971718B (en)
GB (1) GB2481232A (en)
IL (1) IL222671A (en)
MY (1) MY162612A (en)
TW (1) TWI493349B (en)
WO (1) WO2011158012A1 (en)

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Also Published As

Publication number Publication date
TWI493349B (en) 2015-07-21
EP2583182B1 (en) 2014-11-19
IL222671A (en) 2015-11-30
GB201010114D0 (en) 2010-07-21
CN102971718B (en) 2015-12-16
GB2481232A (en) 2011-12-21
US8706965B2 (en) 2014-04-22
EP2583182A1 (en) 2013-04-24
US20110314224A1 (en) 2011-12-22
CN102971718A (en) 2013-03-13
KR101677900B1 (en) 2016-11-21
KR20130114606A (en) 2013-10-17
JP5543022B2 (en) 2014-07-09
JP2013528879A (en) 2013-07-11
IL222671A0 (en) 2012-12-31
WO2011158012A1 (en) 2011-12-22
TW201211777A (en) 2012-03-16

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