MY165677A - Embedded through-silicon-via - Google Patents

Embedded through-silicon-via

Info

Publication number
MY165677A
MY165677A MYPI2011006291A MYPI2011006291A MY165677A MY 165677 A MY165677 A MY 165677A MY PI2011006291 A MYPI2011006291 A MY PI2011006291A MY PI2011006291 A MYPI2011006291 A MY PI2011006291A MY 165677 A MY165677 A MY 165677A
Authority
MY
Malaysia
Prior art keywords
die
substrate
semiconductor
pads
vias
Prior art date
Application number
MYPI2011006291A
Inventor
Choong Kooi Chee
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to MYPI2011006291A priority Critical patent/MY165677A/en
Priority to TW101146178A priority patent/TWI506745B/en
Priority to PCT/US2012/071681 priority patent/WO2013101849A1/en
Publication of MY165677A publication Critical patent/MY165677A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

ELECTRONIC ASSEMBLIES AND THEIR MANUFACTURE ARE DESCRIBED. ONE EMBODIMENT RELATES TO A DEVICE INCLUDING A MULTILAYER SUBSTRATE COMPRISING A PLURALITY OF DIELECTRIC LAYERS AND METAL LAYERS, THE MULTILAYER SUBSTRATE INCLUDING A FIRST SIDE AND A SECOND SIDE. A SEMICONDUCTOR DIE IS EMBEDDED IN THE SUBSTRATE, THE DIE INCLUDING A PLURALITY OF THROUGH-SEMICONDUCTOR-VIAS EXTENDING FROM A FIRST END TO A SECOND END OF THE DIE. THE THROUGH-SEMICONDUCTOR-VIAS ARE ELECTRICALLY COUPLED TO ELECTRICALLY CONDUCTING PATHWAYS DEFINED BY THE METAL LAYERS, INCLUDING PATHWAYS EXTENDING FROM THE FIRST END OF THE DIE TO PADS ON THE FIRST SIDE OF THE SUBSTRATE, AND PATHWAYS EXTENDING FROM THE SECOND END OF THE DIE TO PADS ON THE SECOND SIDE OF THE SUBSTRATE. THE THROUGH-SEMICONDUCTOR-VIAS IN THE DIE HAVE A PITCH THAT IS SMALLER THAN THAT OF THE PADS ON THE FIRST SIDE OF THE SUBSTRATE. THE THROUGH-SEMICONDUCTOR-VIAS IN THE DIE HAVE A PITCH THAT ALSO IS SMALLER THAN THAT OF THE PADS ON THE SECOND SIDE OF THE SUBSTRATE.
MYPI2011006291A 2011-12-27 2011-12-27 Embedded through-silicon-via MY165677A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
MYPI2011006291A MY165677A (en) 2011-12-27 2011-12-27 Embedded through-silicon-via
TW101146178A TWI506745B (en) 2011-12-27 2012-12-07 Electronic device and electronic device manufacturing method
PCT/US2012/071681 WO2013101849A1 (en) 2011-12-27 2012-12-26 Embedded through-silicon-via

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MYPI2011006291A MY165677A (en) 2011-12-27 2011-12-27 Embedded through-silicon-via

Publications (1)

Publication Number Publication Date
MY165677A true MY165677A (en) 2018-04-18

Family

ID=48698594

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2011006291A MY165677A (en) 2011-12-27 2011-12-27 Embedded through-silicon-via

Country Status (3)

Country Link
MY (1) MY165677A (en)
TW (1) TWI506745B (en)
WO (1) WO2013101849A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG11201608947SA (en) * 2014-06-16 2016-11-29 Intel Corp Embedded memory in interconnect stack on silicon die
KR20160090705A (en) * 2015-01-22 2016-08-01 에스케이하이닉스 주식회사 Package substrate, and semiconductor package using the package substrate
CN118173519A (en) 2019-03-11 2024-06-11 奥特斯奥地利科技与系统技术有限公司 Component carrier and method for manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388207B1 (en) * 2000-12-29 2002-05-14 Intel Corporation Electronic assembly with trench structures and methods of manufacture
TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US7049208B2 (en) * 2004-10-11 2006-05-23 Intel Corporation Method of manufacturing of thin based substrate
US7576435B2 (en) * 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
KR100891805B1 (en) * 2007-05-25 2009-04-07 주식회사 네패스 Wafer-level system-in-package and manufacturing method thereof
KR100872583B1 (en) * 2007-07-12 2008-12-08 삼성전기주식회사 Printed Circuit Board Manufacturing Method and Interposer Board
KR20100030151A (en) * 2008-09-09 2010-03-18 삼성전기주식회사 Electronic chip embedded pcb
US20100155931A1 (en) * 2008-12-22 2010-06-24 Qualcomm Incorporated Embedded Through Silicon Stack 3-D Die In A Package Substrate
TWI460844B (en) * 2009-04-06 2014-11-11 金龍國際公司 Stacked package structure with embedded wafer and germanium via film and manufacturing method thereof
KR101084910B1 (en) * 2009-10-12 2011-11-17 삼성전기주식회사 Electronic component embedded printed circuit board and manufacturing method

Also Published As

Publication number Publication date
WO2013101849A1 (en) 2013-07-04
TWI506745B (en) 2015-11-01
TW201342550A (en) 2013-10-16

Similar Documents

Publication Publication Date Title
PH12014000026A1 (en) Semiconductor component and method of manufacture
EP2654388A3 (en) Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package
HK1204421A1 (en) Method and system for producing a multilayer element and multilayer element
TW201613053A (en) Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication
EP2779231A3 (en) Power overlay structure and method of making same
EP3010038A3 (en) Power overlay structure having wirebonds and method of manufacturing same
WO2012037216A3 (en) Staged via formation from both sides of chip
WO2012074783A3 (en) Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same
GB2509810A (en) Stretchable circuit assemblies
TW201613066A (en) Package-on-package options with multiple layer 3-D stacking
JP2015502021A5 (en)
EP2779230A3 (en) Power overlay structure and method of making same
MX2016014825A (en) Energy storage device and method of production thereof.
WO2012143784A3 (en) Semiconductor device and manufacturing method thereof
EP2571051A3 (en) Power overlay structure with leadframe connections
WO2012091487A3 (en) Electrode, and electronic device comprising same
GB2482039B (en) Electronic device
WO2012050333A3 (en) Radiant heat circuit board, method of manufacturing the same, heat generating device package having the same, and backlight
ITMI20111846A1 (en) PROCEDURE FOR PRODUCING AN ELECTRICAL CIRCUIT AND ELECTRIC CIRCUIT
WO2012175207A3 (en) Electronic assembly and method for the production thereof
GB2532869A (en) Semiconductor die and package jigsaw submount
SG10201401166YA (en) Integrated circuit packaging system with embedded pad on layered substrate and method of manufacture thereof
PH12013000046A1 (en) Laminated inductor
MY170565A (en) Contactless chip card
EP2752880A3 (en) Graphene electronic devices and methods of manufacturing the same