MY169590A - Method of fabricating nano-resistors - Google Patents

Method of fabricating nano-resistors

Info

Publication number
MY169590A
MY169590A MYPI2010700005A MYPI2010700005A MY169590A MY 169590 A MY169590 A MY 169590A MY PI2010700005 A MYPI2010700005 A MY PI2010700005A MY PI2010700005 A MYPI2010700005 A MY PI2010700005A MY 169590 A MY169590 A MY 169590A
Authority
MY
Malaysia
Prior art keywords
nano
structures
resistors
polysilicon
fabricating
Prior art date
Application number
MYPI2010700005A
Inventor
Bien Chia Sheng Daniel
Mohd Zain Azlina
Hing Wah Lee
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Priority to MYPI2010700005A priority Critical patent/MY169590A/en
Priority to PCT/MY2010/000317 priority patent/WO2011096790A2/en
Publication of MY169590A publication Critical patent/MY169590A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The present invention describes a novel method of fabricating nano-resistors (22) which allows full integration with standard CMOS fabrication process. The resistor comprises long and thin nano-structures as resistive element. It is formed by conductive nano-spacers (18B) using oxide (16) as mould on insulating layer. An embodiment of such structure is polysilicon nano-structures doped or implanted with n-type or p-type ions (20) to improve material conductance. The electrical properties of the device will change with respect to the dimension of these nano-structures. Resistors with polysilicon nano-structures down to 10 nm can be produced with resulting measured resistance in the MOhm scale.
MYPI2010700005A 2010-02-02 2010-02-02 Method of fabricating nano-resistors MY169590A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
MYPI2010700005A MY169590A (en) 2010-02-02 2010-02-02 Method of fabricating nano-resistors
PCT/MY2010/000317 WO2011096790A2 (en) 2010-02-02 2010-12-13 Method of fabricating nano-resistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MYPI2010700005A MY169590A (en) 2010-02-02 2010-02-02 Method of fabricating nano-resistors

Publications (1)

Publication Number Publication Date
MY169590A true MY169590A (en) 2019-04-22

Family

ID=44356022

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2010700005A MY169590A (en) 2010-02-02 2010-02-02 Method of fabricating nano-resistors

Country Status (2)

Country Link
MY (1) MY169590A (en)
WO (1) WO2011096790A2 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6611039B2 (en) * 2001-09-28 2003-08-26 Hewlett-Packard Development Company, L.P. Vertically oriented nano-fuse and nano-resistor circuit elements
KR20030096705A (en) * 2002-06-17 2003-12-31 주식회사 하이닉스반도체 Method for froming gate of semiconductor device
US6566280B1 (en) * 2002-08-26 2003-05-20 Intel Corporation Forming polymer features on a substrate
KR20050073320A (en) * 2004-01-09 2005-07-13 매그나칩 반도체 유한회사 Method for forming various pitch pattern of nano space
US7390746B2 (en) * 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US20090311634A1 (en) * 2008-06-11 2009-12-17 Tokyo Electron Limited Method of double patterning using sacrificial structure

Also Published As

Publication number Publication date
WO2011096790A3 (en) 2011-11-10
WO2011096790A2 (en) 2011-08-11

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