MY173537A - Manufacturing apparatus and manufacturing method - Google Patents

Manufacturing apparatus and manufacturing method

Info

Publication number
MY173537A
MY173537A MYPI2016700554A MYPI2016700554A MY173537A MY 173537 A MY173537 A MY 173537A MY PI2016700554 A MYPI2016700554 A MY PI2016700554A MY PI2016700554 A MYPI2016700554 A MY PI2016700554A MY 173537 A MY173537 A MY 173537A
Authority
MY
Malaysia
Prior art keywords
cut
qfn
along
qfn substrate
substrate
Prior art date
Application number
MYPI2016700554A
Inventor
Okamoto Jun
Original Assignee
Towa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Towa Corp filed Critical Towa Corp
Publication of MY173537A publication Critical patent/MY173537A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0428—Apparatus for mechanical treatment or grinding or cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Dicing (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

A QFN substrate (2) is cut at three stages along a plurality of cutting lines (9, 10) set in a grid pattern in the QFN substrate (2). First, on the cutting lines (9) along the longer direction of the QFN substrate (2), a portion substantially corresponding to a thickness of a tie bar (6) of a lead frame (2) is cut, thereby forming cut trenches (23). Next, on the cutting lines (10) along the shorter direction of the QFN substrate (2), the lead frame (2) and a sealing resin (8) are collectively cut. Next, on the cut trenches (23) along the longer direction (9) of the QFN substrate (2), a portion corresponding to a remaining thickness of the sealing resin (8) is cut. Since only the portion of the sealing resin (8) is cut on the cut trenches (23), the processing load when the QFN substrate (2) is finally divided into QFN products (13) can be reduced. Therefore, it is possible to prevent the QFN product (13) from being displaced or scattered from a prescribed position of a cutting jig (15).
MYPI2016700554A 2015-03-04 2016-02-17 Manufacturing apparatus and manufacturing method MY173537A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015042803A JP6525643B2 (en) 2015-03-04 2015-03-04 Manufacturing apparatus and manufacturing method

Publications (1)

Publication Number Publication Date
MY173537A true MY173537A (en) 2020-02-03

Family

ID=56847225

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2016700554A MY173537A (en) 2015-03-04 2016-02-17 Manufacturing apparatus and manufacturing method

Country Status (5)

Country Link
JP (1) JP6525643B2 (en)
KR (1) KR101779701B1 (en)
CN (1) CN105938808B (en)
MY (1) MY173537A (en)
TW (1) TWI618193B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6800745B2 (en) * 2016-12-28 2020-12-16 株式会社ディスコ Semiconductor package manufacturing method
JP7043346B2 (en) * 2018-05-18 2022-03-29 株式会社ディスコ Cutting equipment
JP2020088262A (en) * 2018-11-29 2020-06-04 株式会社ディスコ Package board dividing method

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2592489B2 (en) * 1988-03-18 1997-03-19 富士通株式会社 Wafer dicing method
JPH0574932A (en) * 1991-09-17 1993-03-26 Fujitsu Ltd Semiconductor wafer dicing method
JP3229035B2 (en) * 1992-09-25 2001-11-12 ローム株式会社 Silicon wafer cutting method
JP3521325B2 (en) 1999-07-30 2004-04-19 シャープ株式会社 Manufacturing method of resin-encapsulated semiconductor device
JP2002343817A (en) 2001-05-11 2002-11-29 Tomoegawa Paper Co Ltd Semiconductor device unit
JP2003031526A (en) * 2001-07-16 2003-01-31 Mitsumi Electric Co Ltd Module manufacturing method and module
JP2006222359A (en) * 2005-02-14 2006-08-24 Hitachi Cable Ltd Method for manufacturing light-emitting diode array
US7694688B2 (en) * 2007-01-05 2010-04-13 Applied Materials, Inc. Wet clean system design
JP2009170501A (en) * 2008-01-11 2009-07-30 Disco Abrasive Syst Ltd Cutting equipment
JP2011035142A (en) * 2009-07-31 2011-02-17 Sanyo Electric Co Ltd Method of manufacturing circuit device
US8801307B2 (en) * 2009-09-25 2014-08-12 Nikon Corporation Substrate cartridge, substrate processing apparatus, substrate processing system, control apparatus, and method of manufacturing display element
JP2011159679A (en) * 2010-01-29 2011-08-18 Furukawa Electric Co Ltd:The Method of manufacturing chip
JP2011211159A (en) * 2010-03-10 2011-10-20 Renesas Electronics Corp Method for manufacturing semiconductor device
US9349679B2 (en) * 2010-08-31 2016-05-24 Utac Thai Limited Singulation method for semiconductor package with plating on side of connectors
JP5899614B2 (en) * 2010-11-26 2016-04-06 大日本印刷株式会社 Leadframe and leadframe manufacturing method
JP2013069814A (en) * 2011-09-21 2013-04-18 Renesas Electronics Corp Method for manufacturing semiconductor device
JP5897454B2 (en) * 2012-12-03 2016-03-30 Ｔｏｗａ株式会社 Cutting apparatus and method for manufacturing electronic parts
JP6111168B2 (en) * 2013-08-23 2017-04-05 株式会社ディスコ Package substrate division method

Also Published As

Publication number Publication date
JP2016162973A (en) 2016-09-05
KR20160108170A (en) 2016-09-19
CN105938808A (en) 2016-09-14
TWI618193B (en) 2018-03-11
CN105938808B (en) 2018-10-26
JP6525643B2 (en) 2019-06-05
KR101779701B1 (en) 2017-10-10
TW201701409A (en) 2017-01-01

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