MY192589A - Wiring substrate, method for manufacturing wiring substrate, electronic component, and method for manufacturing electronic component - Google Patents
Wiring substrate, method for manufacturing wiring substrate, electronic component, and method for manufacturing electronic componentInfo
- Publication number
- MY192589A MY192589A MYPI2019000001A MYPI2019000001A MY192589A MY 192589 A MY192589 A MY 192589A MY PI2019000001 A MYPI2019000001 A MY PI2019000001A MY PI2019000001 A MYPI2019000001 A MY PI2019000001A MY 192589 A MY192589 A MY 192589A
- Authority
- MY
- Malaysia
- Prior art keywords
- wiring substrate
- electronic component
- manufacturing
- layer
- conductor portions
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
A wiring substrate (1) includes a first layer (100) and a second layer (200) on one surface of the first layer (100). The first layer (100) includes a plurality of first conductor portions (6) and a resin portion (3) disposed between the plurality of first conductor portions (6) to electrically isolate the plurality of first conductor portions (6). The second layer (200) includes a plurality of second conductor portions (4) in contact with the plurality of first conductor portions (6), respectively, and electrically isolated from each other. The plurality of second conductor portions (4) are each in contact with the resin portion (3) on a portion of a surface of the second conductor portion (4) closer to the first layer (100). Figure 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016136037A JP6333894B2 (en) | 2016-07-08 | 2016-07-08 | Wiring board, wiring board manufacturing method, electronic component, and electronic component manufacturing method |
| PCT/JP2017/014101 WO2018008214A1 (en) | 2016-07-08 | 2017-04-04 | Wiring board, method for manufacturing wiring board, electronic component, and method for manufacturing electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| MY192589A true MY192589A (en) | 2022-08-29 |
Family
ID=60912065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MYPI2019000001A MY192589A (en) | 2016-07-08 | 2017-04-04 | Wiring substrate, method for manufacturing wiring substrate, electronic component, and method for manufacturing electronic component |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JP6333894B2 (en) |
| KR (1) | KR102254999B1 (en) |
| CN (1) | CN109478536A (en) |
| MY (1) | MY192589A (en) |
| TW (1) | TWI650051B (en) |
| WO (1) | WO2018008214A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003303859A (en) * | 2002-04-10 | 2003-10-24 | Hitachi Cable Ltd | Tape carrier for semiconductor device and method of manufacturing the same |
| US7164192B2 (en) * | 2003-02-10 | 2007-01-16 | Skyworks Solutions, Inc. | Semiconductor die package with reduced inductance and reduced die attach flow out |
| JP2005116909A (en) * | 2003-10-10 | 2005-04-28 | Hitachi Cable Ltd | Electronic device and wiring board used in electronic device |
| JP2011029518A (en) * | 2009-07-28 | 2011-02-10 | Shindo Denshi Kogyo Kk | Flexible printed wiring board, semiconductor device, and method for manufacturing the same |
| JP5848976B2 (en) * | 2012-01-25 | 2016-01-27 | 新光電気工業株式会社 | WIRING BOARD, LIGHT EMITTING DEVICE, AND WIRING BOARD MANUFACTURING METHOD |
-
2016
- 2016-07-08 JP JP2016136037A patent/JP6333894B2/en active Active
-
2017
- 2017-04-04 WO PCT/JP2017/014101 patent/WO2018008214A1/en not_active Ceased
- 2017-04-04 MY MYPI2019000001A patent/MY192589A/en unknown
- 2017-04-04 KR KR1020187036756A patent/KR102254999B1/en active Active
- 2017-04-04 CN CN201780042267.9A patent/CN109478536A/en active Pending
- 2017-04-10 TW TW106111861A patent/TWI650051B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| TW201804881A (en) | 2018-02-01 |
| TWI650051B (en) | 2019-02-01 |
| JP6333894B2 (en) | 2018-05-30 |
| WO2018008214A1 (en) | 2018-01-11 |
| CN109478536A (en) | 2019-03-15 |
| JP2018006702A (en) | 2018-01-11 |
| KR102254999B1 (en) | 2021-05-24 |
| KR20190025835A (en) | 2019-03-12 |
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