MY197461A - Conductor path structure, in particular for a lead frame for a smart card application, with at least two superimposed conductor path planes - Google Patents
Conductor path structure, in particular for a lead frame for a smart card application, with at least two superimposed conductor path planesInfo
- Publication number
- MY197461A MY197461A MYPI2018001899A MYPI2018001899A MY197461A MY 197461 A MY197461 A MY 197461A MY PI2018001899 A MYPI2018001899 A MY PI2018001899A MY PI2018001899 A MYPI2018001899 A MY PI2018001899A MY 197461 A MY197461 A MY 197461A
- Authority
- MY
- Malaysia
- Prior art keywords
- conductor path
- conductor
- path
- planes
- paths
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07718—Constructional details, e.g. mounting of circuits in the carrier the record carrier being manufactured in a continuous process, e.g. using endless rolls
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/699—Insulating or insulated package substrates; Interposers; Redistribution layers for flat cards, e.g. credit cards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09136—Means for correcting warpage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10287—Metal wires as connectors or conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
- Geometry (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention relates to a conductor path structure, in particular for a lead- frame for a smart card application, which comprises at least one first con-ductor path plane (10) with several first conductor paths (11; 11a-11f) and at least one second conductor path plane (20) with several second conductor paths (21; 21a-21f). Superimposed conductor path planes (10, 20) are sepa-rated by an insulator (30), at least one first conductor path (11, 11a, 11b, 11c, 11d, 11f) of the first conductor path plane (10) comprises at least one through-extending connection opening (12; 12a-12e), through which a con-nection wire can be guided and can be placed in electrically conductive con- tact with the conductor path (21; 21a-21f) of the second conductor path planes (20). At least two adjacent conductor paths (11; 11a, 11b; 11b, 11c; 11d, 11e; 11e, 11f) of the first conductor path plane (10) are separated from each other by slots (13; 13a-13i) and at least two adjacent conductor paths (21a, 21b; 21b, 21c, 21d, 21e; 21e, 21f) are separated from each other by further slots (23a-23e). According to the invention, the slots (13; 13a-13i) separating one or more adjacent conductor paths (11; 11, 11a, 11b, 11c, 11d, 11f) of the first conductor path plane (10) and other slots (11 or 23) separating the adjacent conductor paths (21; 21a-21f) of the second conduc-tor path plane (20) are arranged offset to each other. [Fig. 1]
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE202016002993.3U DE202016002993U1 (en) | 2016-05-11 | 2016-05-11 | Conductor structure, in particular for a lead frame for a smart card application, with at least two superimposed interconnect levels |
| DE102016005657.6A DE102016005657A1 (en) | 2016-05-11 | 2016-05-11 | Conductor structure, in particular for a lead frame for a smart card application, with at least two superimposed interconnect levels |
| PCT/EP2017/025118 WO2017194200A2 (en) | 2016-05-11 | 2017-05-10 | Conductor path structure, in particular for a lead frame for a smart card application, with at least two superimposed conductor path planes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| MY197461A true MY197461A (en) | 2023-06-19 |
Family
ID=59021451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MYPI2018001899A MY197461A (en) | 2016-05-11 | 2017-05-10 | Conductor path structure, in particular for a lead frame for a smart card application, with at least two superimposed conductor path planes |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP3456160B1 (en) |
| KR (1) | KR102267167B1 (en) |
| CN (1) | CN109315064B (en) |
| MY (1) | MY197461A (en) |
| SG (1) | SG11201809748RA (en) |
| WO (1) | WO2017194200A2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10763203B1 (en) | 2019-02-08 | 2020-09-01 | Nxp B.V. | Conductive trace design for smart card |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3452678B2 (en) * | 1995-03-03 | 2003-09-29 | 三菱電機株式会社 | Manufacturing method of wiring structure |
| DE19703057A1 (en) * | 1996-12-20 | 1998-07-02 | Siemens Ag | Carrier element for semiconductor chip esp. for combination chip card |
| DE19816066A1 (en) * | 1998-04-09 | 1999-10-14 | Philips Patentverwaltung | Foil as a carrier for integrated circuits |
| ATE440346T1 (en) * | 2005-11-14 | 2009-09-15 | Tyco Electronics France Sas | SMARTCARD BODY, SMARTCARD AND MANUFACTURING METHOD |
| CN101841734B (en) * | 2009-03-16 | 2012-11-07 | 华为技术有限公司 | Back plate and back plate communication system |
-
2017
- 2017-05-10 CN CN201780038143.3A patent/CN109315064B/en active Active
- 2017-05-10 SG SG11201809748RA patent/SG11201809748RA/en unknown
- 2017-05-10 MY MYPI2018001899A patent/MY197461A/en unknown
- 2017-05-10 WO PCT/EP2017/025118 patent/WO2017194200A2/en not_active Ceased
- 2017-05-10 EP EP17728449.4A patent/EP3456160B1/en active Active
- 2017-05-10 KR KR1020187035182A patent/KR102267167B1/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR20190010866A (en) | 2019-01-31 |
| KR102267167B1 (en) | 2021-06-23 |
| CN109315064A (en) | 2019-02-05 |
| EP3456160B1 (en) | 2019-07-03 |
| WO2017194200A3 (en) | 2018-01-11 |
| CN109315064B (en) | 2021-10-19 |
| EP3456160A2 (en) | 2019-03-20 |
| WO2017194200A2 (en) | 2017-11-16 |
| SG11201809748RA (en) | 2018-12-28 |
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