NO20006698L - Serial data bus protocol between devices - Google Patents

Serial data bus protocol between devices

Info

Publication number
NO20006698L
NO20006698L NO20006698A NO20006698A NO20006698L NO 20006698 L NO20006698 L NO 20006698L NO 20006698 A NO20006698 A NO 20006698A NO 20006698 A NO20006698 A NO 20006698A NO 20006698 L NO20006698 L NO 20006698L
Authority
NO
Norway
Prior art keywords
data
line
clock
serial bus
signal level
Prior art date
Application number
NO20006698A
Other languages
Norwegian (no)
Other versions
NO20006698D0 (en
Inventor
Sanjay K Jha
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of NO20006698D0 publication Critical patent/NO20006698D0/en
Publication of NO20006698L publication Critical patent/NO20006698L/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)

Abstract

Seriebussprotokoll mellom tilkoplede enheter (50, 52, 54) via en seriebuss (48). Seriebussen (48) inneholder en klokkelinje (SBCK), en start/stopplinje (SBST) og en datalinje (SBDT). Et hovedseriebussgrensesnitt (62, 64, 66) kopler en hovedenhet (50) til seriebussen, og et slaveserie- bussgrensesnitt (63, 65, 67) kopler en eller flere slaveenheter (52, 54) til samme. I en særlig utførelse kan hovedseriebussgrensesnittet (180) omfatte en rrans- aksjonsigangsetter, en datainnlesingsmekanisme, en datautlesingsmekanisme og en klokkedrivenhet. Trans- aksjonsigangsetteren setter i gang en transaksjon ved å trekke start/stopplinjens nivå ned. Datainnlesingsmeka- nismen styrer signalnivået på datalinjen ut fra de data som skal leses inn i slaveenheten. Datalesemekanismen leser data ut ved å overvåke signalnivået på datalinjen. Klokkedrivenheten styrer signalnivået på klokkelinjen i samsvar med et ønsket klokkesignal.Serial bus protocol between connected devices (50, 52, 54) via a serial bus (48). The serial bus (48) contains a clock line (SBCK), a start / stop line (SBST) and a data line (SBDT). A main series bus interface (62, 64, 66) connects a main unit (50) to the serial bus, and a slave series bus interface (63, 65, 67) connects one or more slave units (52, 54) to the same. In a particular embodiment, the main series bus interface (180) may comprise a transaction initiator, a data readout mechanism, a data readout mechanism, and a clock drive. The transaction initiator initiates a transaction by subtracting the start / stop line level. The data entry mechanism controls the signal level of the data line based on the data to be read into the slave unit. The data read mechanism reads data by monitoring the signal level on the data line. The clock driver controls the signal level on the clock line according to a desired clock signal.

NO20006698A 1998-07-01 2000-12-29 Serial data bus protocol between devices NO20006698L (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US9138398P 1998-07-01 1998-07-01
US24893999A 1999-02-11 1999-02-11
PCT/US1999/014696 WO2000002134A2 (en) 1998-07-01 1999-06-30 Improved inter-device serial bus protocol

Publications (2)

Publication Number Publication Date
NO20006698D0 NO20006698D0 (en) 2000-12-29
NO20006698L true NO20006698L (en) 2001-02-20

Family

ID=26783906

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20006698A NO20006698L (en) 1998-07-01 2000-12-29 Serial data bus protocol between devices

Country Status (9)

Country Link
EP (1) EP1145132A3 (en)
JP (1) JP2003534580A (en)
KR (1) KR20010053365A (en)
AU (1) AU4843299A (en)
BR (1) BR9911732A (en)
CA (1) CA2336385A1 (en)
IL (1) IL140568A0 (en)
NO (1) NO20006698L (en)
WO (1) WO2000002134A2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7076225B2 (en) * 2001-02-16 2006-07-11 Qualcomm Incorporated Variable gain selection in direct conversion receiver
FR2828947B1 (en) * 2001-08-27 2003-12-19 Pierre Trazic OUT AND IN FUNCTIONS OF CONNECTION ON A UCE BUS
JP4831899B2 (en) * 2001-08-28 2011-12-07 富士通セミコンダクター株式会社 Semiconductor integrated circuit and clock control method
JP2005515547A (en) * 2001-12-28 2005-05-26 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Communications system
DE102005007333B4 (en) * 2004-05-07 2008-07-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Multi-chip packages with high-speed serial communications between semiconductor dies
US7342310B2 (en) 2004-05-07 2008-03-11 Avago Technologies General Ip Pte Ltd Multi-chip package with high-speed serial communications between semiconductor die
US20060031618A1 (en) * 2004-05-20 2006-02-09 Hansquine David W Single wire and three wire bus interoperability
US20050259609A1 (en) 2004-05-20 2005-11-24 Hansquine David W Single wire bus interface
KR100698303B1 (en) * 2005-03-21 2007-03-22 엘지전자 주식회사 Serial bus direction controller
KR100910446B1 (en) 2007-12-03 2009-08-04 주식회사 동부하이텍 Data Synchronization Implementation Circuit and Method of I2C Time Controller for Display Device
WO2011056729A2 (en) 2009-11-05 2011-05-12 Rambus Inc. Interface clock management
US9300129B2 (en) 2013-03-12 2016-03-29 Ascensia Diabetes Care Holding Ag Reverse battery protection for battery-powered devices
WO2015120339A1 (en) * 2014-02-07 2015-08-13 Bayer Healthcare Llc Methods and apparatus for a multiple master bus protocol
US9734121B2 (en) 2014-04-28 2017-08-15 Qualcomm Incorporated Sensors global bus
US10417172B2 (en) 2014-04-28 2019-09-17 Qualcomm Incorporated Sensors global bus
IT201800002767A1 (en) 2018-02-16 2019-08-16 St Microelectronics Srl CIRCUIT FOR LED DRIVING, CORRESPONDING DEVICE AND PROCEDURE

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910509A (en) * 1988-03-17 1990-03-20 Zenith Electronics Corporation Bus expander for digital TV receiver
EP0589499B1 (en) * 1992-08-12 1999-04-07 Koninklijke Philips Electronics N.V. A multistation communication bus system, and a master station and a slave station for use in such system
GB2278259B (en) * 1993-05-21 1997-01-15 Northern Telecom Ltd Serial bus system

Also Published As

Publication number Publication date
CA2336385A1 (en) 2000-01-13
EP1145132A2 (en) 2001-10-17
NO20006698D0 (en) 2000-12-29
EP1145132A3 (en) 2002-08-21
WO2000002134A3 (en) 2001-09-27
KR20010053365A (en) 2001-06-25
WO2000002134A2 (en) 2000-01-13
IL140568A0 (en) 2002-02-10
BR9911732A (en) 2002-01-29
JP2003534580A (en) 2003-11-18
AU4843299A (en) 2000-01-24

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