NO20042541L - Basestasjon som har et hybrid parallell/serie buss grensesnitt - Google Patents

Basestasjon som har et hybrid parallell/serie buss grensesnitt

Info

Publication number
NO20042541L
NO20042541L NO20042541A NO20042541A NO20042541L NO 20042541 L NO20042541 L NO 20042541L NO 20042541 A NO20042541 A NO 20042541A NO 20042541 A NO20042541 A NO 20042541A NO 20042541 L NO20042541 L NO 20042541L
Authority
NO
Norway
Prior art keywords
serial
data block
nibble
base station
bus interface
Prior art date
Application number
NO20042541A
Other languages
English (en)
Inventor
Timothy A Axness
Joseph Gredone
Alfred Stufflet
Original Assignee
Interdigital Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/990,060 external-priority patent/US7069464B2/en
Application filed by Interdigital Tech Corp filed Critical Interdigital Tech Corp
Publication of NO20042541L publication Critical patent/NO20042541L/no

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Traffic Control Systems (AREA)
  • Train Traffic Observation, Control, And Security (AREA)
  • Small-Scale Networks (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Et hybrid serie/parallellbussgrensesnitt for en basestasjon har en. datablokkdemultipleksinganordning. Datablokkdemultipleksinganordningen har en inngang konfigurert for å motta en datablokk og demultiplekser datablokken i et mangfold av nibler. For hver nible omformer en parallell til serie omformer niblen til seriedata. En linje overfører hver nibles seriedata. En serie til parallellomformer omformer hver nibles seriedata for å gjenvinne denne niblen. En datablokkrekonstruksjonsanordning kombinerer de gjenvunnede niblene i datablokken.
NO20042541A 2001-11-21 2004-06-17 Basestasjon som har et hybrid parallell/serie buss grensesnitt NO20042541L (no)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/990,060 US7069464B2 (en) 2001-11-21 2001-11-21 Hybrid parallel/serial bus interface
US10/081,466 US6829718B2 (en) 2001-11-21 2002-02-22 Base station having a hybrid parallel/serial bus interface
PCT/US2002/037150 WO2003046391A2 (en) 2001-11-21 2002-11-19 Base station having a hybrid parallel/serial bus interface

Publications (1)

Publication Number Publication Date
NO20042541L true NO20042541L (no) 2004-07-26

Family

ID=26765598

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20042541A NO20042541L (no) 2001-11-21 2004-06-17 Basestasjon som har et hybrid parallell/serie buss grensesnitt

Country Status (12)

Country Link
EP (1) EP1446584B1 (no)
JP (2) JP4142584B2 (no)
CN (1) CN1332328C (no)
AT (1) ATE367681T1 (no)
AU (1) AU2002352801A1 (no)
CA (1) CA2467632A1 (no)
DE (1) DE60221270T2 (no)
ES (1) ES2287345T3 (no)
MX (1) MXPA04004790A (no)
NO (1) NO20042541L (no)
TW (1) TWI267274B (no)
WO (1) WO2003046391A2 (no)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4546416B2 (ja) * 2006-04-24 2010-09-15 ザインエレクトロニクス株式会社 画像信号受信装置
CN105242591B (zh) * 2015-08-17 2017-12-12 合肥宝龙达信息技术有限公司 一种输入输出接口合并系统
CN108736897B (zh) * 2018-04-26 2022-08-09 深圳市国微电子有限公司 应用于高速接口物理层芯片的并串转换电路及装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2822815B2 (ja) * 1992-09-30 1998-11-11 日本電気株式会社 基地局間信号伝送方式
US5602780A (en) * 1993-10-20 1997-02-11 Texas Instruments Incorporated Serial to parallel and parallel to serial architecture for a RAM based FIFO memory
KR100186229B1 (ko) * 1995-12-08 1999-05-15 김광호 타임스위칭 및 회의통화 기능 통합 구현장치
US5812881A (en) * 1997-04-10 1998-09-22 International Business Machines Corporation Handshake minimizing serial to parallel bus interface in a data processing system
JP2001136156A (ja) * 1999-11-08 2001-05-18 Toshiba Digital Media Engineering Corp データ伝送速度変換回路

Also Published As

Publication number Publication date
EP1446584A2 (en) 2004-08-18
DE60221270D1 (de) 2007-08-30
TWI267274B (en) 2006-11-21
JP4142584B2 (ja) 2008-09-03
TW200303673A (en) 2003-09-01
CA2467632A1 (en) 2003-06-05
MXPA04004790A (es) 2004-08-11
AU2002352801A8 (en) 2003-06-10
WO2003046391A2 (en) 2003-06-05
WO2003046391A3 (en) 2003-10-09
JP2008011577A (ja) 2008-01-17
ATE367681T1 (de) 2007-08-15
AU2002352801A1 (en) 2003-06-10
ES2287345T3 (es) 2007-12-16
HK1073701A1 (en) 2005-10-14
JP2005510915A (ja) 2005-04-21
CN1332328C (zh) 2007-08-15
DE60221270T2 (de) 2008-04-10
EP1446584A4 (en) 2005-05-11
EP1446584B1 (en) 2007-07-18
CN1610891A (zh) 2005-04-27

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Legal Events

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