NO851692L - LINE CIRCUIT - Google Patents

Description

The present invention relates to electronic contacts which make it possible to establish a low or a high impedance between a first and a second terminal under the control of a circuit which generates a control signal between a third and a fourth terminal.

Such electronic contacts are e.g. used in Belgian patent no. 896 388 and then particularly in connection with a controlled capacitive charging circuit which makes it possible to charge a capacitor positively or negatively, and this will, depending on the sign of its landing, open or close an electronic contact consisting of two DMOS transistors in reverse-coupled connection (in series-opposition, in such a way that their drain electrodes respectively constitute the two terminals of the electronic connector while their source electrodes are both connected to the same terminal of the capacitor, and their gate electrodes are both connected to the other terminals of the capacitor, and where it is possible for the capacitor to be made up of the parasitic capacitance between the terminal pairs. In this way, by using transistors to withstand the relatively high voltages, an electronic contact is achieved which can be introduced into a circuit where different polarities can appear at the contact terminals In reality it will be the case that when the polarity of the charge on the control cone densator for the contact is such that it does not exhibit a low resistance path, i.e. the two transistors are blocked, the parasitic diodes that appear for this transistor state between the source and drain electrodes will also be connected in reverse, or series opposition, direction, and this maintains a high impedance regardless of the polarity supplied by the circuit into which the connector is inserted.

One of the purposes of the present invention is to enable the use of a more appropriate electronic contact which can also be controlled by the polarity of the charge of a capacitor, and in particular thyristor equipment which is able to work under high voltages e.g. 300 V) as foreshadowed in the above-mentioned patent, but which can only send current in one direction while they can block voltages of one or the other polarity, and that the transistors of the above-mentioned patent have inverse properties, i.e. they can conduct the current in one direction or the other, but only block one voltage polarity.

Generally speaking, the purpose of the present invention is to enable the use of such electronic contacts while avoiding complications of the control circuit.

This is achieved by designing the electronic contact in accordance with the patent claims set out below.

Such an arrangement leads to the advantage that two electronic contacts of the thyristor type can be connected to each other top to bottom like a triac and controlled v.hj.a. same control circuit, and in particular a control circuit according to the above-mentioned patent which makes use of a positive or negative charging of a capacitor to close or open the electronic contact. By means of the auxiliary contacts, it will in fact be possible, in accordance with the polarity of the voltage supplied to the terminals of the electronic contact constituted by the two biased contacts connected in shunt opposition, to automatically achieve

a connection between a terminal of the control capacitor and the terminal of the main electronics connector with a given polarity. In this way, the same capacitor charging circuit, i.e. the voltage doubler AC/DC converter described in the above-mentioned patent, will always be able to be used to close or open the one of the two polarized contacts effectively introduced into a load circuit and depending on the polarity of the voltage that appears at the terminals of these contacts connected in shunt opposition.

On the other hand, the advantage of thyristor-equipped electronic contacts that are able to be controlled in the indicated manner, compared to DMOS transistors connected in series opposition as in the above-mentioned Belgian patent instead of the proposed top to bottom connection, will be that the resistance of the contact in the closed state is significantly smaller, e.g. below 10 ohms instead of 25 + 25 = 50 ohms. In addition, the required area for an integrated circuit with the thyristor solution will be reduced to a quarter.

The present invention also relates to an electronic power-reducing device which forms part of a circuit which also comprises a power source and a load, which power-reducing device comprises aids to limit the power losses in the circuit.

Such a disturbance is already known, e.g. from PCT patent application WO 82/03733. There, the power-limiting equipment is constructed so that it will produce a current-voltage characteristic that starts from the origin, rises to a maximum current at a predetermined voltage, stays at this current value until a maximum voltage is reached, and then suddenly drops to a current that is practically equal to 0. At the last breaking point on this characteristic, the power loss in the equipment is a maximum (maximum current and voltage) and in some connections this can be an unacceptably high value, such as e.g. in the case where the equipment is to be integrated on an electronic chip.

One purpose of the present invention is to provide an electronic device of the above type, but with reduced power consumption. This is achieved by designing the equipment in accordance with the patent claims set out below.

The smallest power consumption in the equipment occurs at its operating point, i.e. the point where the current-voltage characteristic crosses the load line. Unwanted abnormal signals from various sources, such as lightning strikes affecting such a telephone circuit or incorrect interconnection with the power supply network may affect the characteristics of the circuit. In reality, such signals are added to the normal signals generated by the power source so that the position of the load line in the diagram is modified. The operating point then moves along the part of the current-voltage characteristic that crosses the load line. If these unwanted abnormal signals become very large, the load line can be shifted in such a way that the operating point reaches the upper end of the portion of the current-voltage characteristic. This operating point then becomes unstable and moves towards higher voltages. Because the current-voltage characteristic then follows the load line, the power lost in the equipment during this displacement of the operating point is reduced to a minimum. When the unwanted, abnormal signals disappear, the operating line will return to the position originally mentioned, and because the part of the current-voltage characteristic that follows the load line does not cross it, the operating point will move from higher voltages to its original position. This would not be the case if there was a crossover between the relevant part of the current-voltage characteristic and the load line. In reality, such a crossing would create a working point that was separate from the above-mentioned working point and affect the normal operating conditions of the electronic equipment.

A further object of the present invention is to allow, at least for relatively low voltages, currents that are much stronger than the short-circuit current flowing through the electronic equipment while maintaining the advantages mentioned above, which apply to higher voltages. This is achieved by designing the electronic equipment in accordance with claim 12 below.

The operating point of the equipment can thus move along the first part of the current-voltage characteristic so that the current in this equipment can reach relatively high values for small voltages without affecting the power-limiting equipment. For higher voltage values, the equipment functions as described above.

A further purpose of the present invention is also to use such electronic contacts in telecommunications systems and then particularly in telephone line circuits to enable various monitoring and control operations, including the provision of ring current, as these have been functions that were previously mainly carried out via relay contacts even in switchboards where the rest of the equipment was electronic.

Thus, the invention also relates to a telecommunications line circuit which comprises a series impedance in each of the two line conductors and contacts on both sides of these two impedances which make it possible to selectively connect their terminals to the switchboard or the line or vice versa, or possibly to the auxiliary circuits.

Such a system is described e.g. in an article published on pages 316 to 324 of the June 1983 IEEE Journal of Solid State Circuits, and particular reference should be made to page 317. Here it appears that the two series resistors serve to feed the subscriber line and also to measure the voltage appearing across these adversaries, and the purpose is monitoring and control operations. On the central side of these resistors, a ring circuit can be introduced v.hj.a. the corresponding contacts and by measuring the voltages across the resistors, one can in this way monitor the ringing operation. Secondly, on the other side of these resistors, the contacts facing the subscriber line enable access to buses for carrying out tests, either internally (toward the switchboard and through the series resistors) or externally to the subscriber line. Until now, these contacts were usually realized v.hj.a. changeover contacts on three relays which automatically caused the closing part of the contact to be connected in shunt with one of the control circuits, while the breaking part, which was in series with one of the resistors, was automatically open, and vice versa.

According to another feature of the present invention, these contacts consist of four pairs of electronic contacts, where the first connects the line to the impedances, the second connects these to the exchange, the third connects the impedances to the line side of the first auxiliary circuit, and the fourth connects it on the central side with a second auxiliary circuit.

According to a further feature of the invention, the control equipment for the four pairs of electronic contacts comprises a decoder capable of being fed by three binary signals in parallel and producing four binary output signals for controlling the four pairs of electronic contacts, one binary selection circuit which is additionally equipped to enable blocking of the decoder output, and in this last case enable connections which allow the four binary input signals to respectively control the four pairs of electronic contacts.

For further features of the present invention, reference is made to the patent claims below.

In this way, it becomes particularly possible to realize the present invention on a single integrated circuit, as not only a series of 8 contacts which are able to withstand relatively high voltages and can operate in pairs, can thereby be placed on the circuit, but also the control operations for these electronic contacts either v.hj.a. a code that only includes three binary elements or direct v.hj.a. a signal corresponding to the pair of electronic contacts.

This versatility can be further increased by incorporating into such an electronic circuit a clock that makes it possible to control the circuits with electronic contacts in a manner described in the above-mentioned patent, thus avoiding having to rely on a single separate clock circuit.

To provide a clearer understanding of the present invention, reference is made to the detailed description of preferred below

execution examples and to the accompanying drawings, where:

- fig. 1 shows the circuit of an electronic contact in accordance with the present invention, - fig. 2 shows the control circuit for the electronic contact according to the above patent, but modified according to

present invention,

- fig. 3 shows part of a telephone line circuit comprising 8 electronic contacts in accordance with the present

invention,

- fig. 4 shows all circuits needed to control the 8 electronic contacts, according to what is shown in block form in

fig. 3,

- fig. 5 shows a protection circuit for the input, which is only shown in block form in fig. 4, - fig. 6 shows an electronic gate which is only shown as a block in FIG. 4, - fig. 7 shows a double electronic gate control v.hj.a. clock pulses, and this is only shown as a block in fig. 4, - fig. 8 shows the circuit which generates the clock pulses and which is shown as a block in fig. 4, - fig. 9 shows a first logic circuit used to realize the decoder which is shown as a block in fig. 4, and - fig. 10 shows a second logic circuit used in this decoder, -fig. 11 shows another embodiment of the circuit of an electronic contact according to fig. 1, comprehensive protection circuits

for the power supply according to the present invention,

- figures 12 and 13 show current-voltage characteristics for the power protection circuits in fig. 11, it should be noted that

the characteristics are not drawn to scale,

- fig. 14 shows current-voltage characteristics for the electronic contact shown in fig. 11, and the characteristics are

here not drawn to scale,

- fig. 15 shows a fault indication circuit FC which is connected to the power protection circuits shown in figure 11 and also in figure 3.

The electronic contact which is able to withstand relatively high voltages and is shown in fig. 1, can be part of an assembly comprising 8 identical electronic contacts (fig. 3) arranged as four contact pairs, where the two contacts in a pair are always simultaneously open or respectively closed, and this combination is suitable for use in telephone subscriber line- circuits and in particular as described in Belgian patent no. 896 468. Apart from the 8 electronic contacts which correspond to what

is shown in fig. 1, and the 8 circuits for such contacts that appear in fig. 2, and essentially corresponding to the controlled capacitive storage circuit of Belgian Patent No. 896,388, Fig. 4 represents a decoder capable of being activated either by three or by four binary signals. In the first case, the eight possible combinations of the three binary signals are decoded on four output terminals, which are respectively used to control the four pairs of electronic contacts. In the second case, the standby signal ensures that the four input signals of binary form are respectively supplied to the four electronic ports, while the same signals block the operation of the decoder. Furthermore, the circuit in fig. 4 at the output of the decoder a converter which is intended to produce suitable signals for the capacitive charging circuit in fig. 2, and this v.hj.a. an oscillator that provides complementary clock pulses.

The five parts identified above, ie the electronic contacts, the control circuit, the decoder, the converter and the oscillator, can be arranged in a common integrated circuit combining a DCMOS low voltage logic contact and TRIMOS high voltage contacts. The manufacturing technique can in particular make use of the processes described in Belgian patent no. 897 139. The entire circuit will then comprise four pairs of electronic contacts capable of blocking voltages of 300 Vi in two directions and with a dynamic resistance of 10 ohms when they is conductive, and the two terminals of each electronic connector are floating with respect to the control circuit. The four contact pairs can be operated in accordance with the 16 possible combinations v.hj.a. four binary signals or in accordance with eight predetermined states v.hj.a. three binary signals.

Now look at fig. 1 it appears that the electronic contact comprises two identical parts S and S' in such a way that only the first is shown in detail. Under the influence of the control signal, the circuit S can either produce a low or a high impedance between its two output terminals Sl and S2, and to these the corresponding terminals S'2 and S'l are connected to S<1>, and the two circuits are thus connected in a connection which will be called anti-shunt. This makes it possible to let them work under three different conditions: Both S and S' present a high impedance between their terminals, S presents a low impedance for a voltage polarity at the terminal of the contact, while S<1> can also present this low impedance , but then for the opposite polarity.

The circuit S is of the TRIMOS type and mainly consists of a transistor Tl of the PNP type connected to a transistor T2 of the NPN type so that it forms a thyristor between terminals Sl and S2. The manufacture of such equipment usually entails the occurrence of a parasitic transistor T3 of the PNP type which is connected in parallel with the first two. This thyristor combination is controlled by the transistor N of the DMOS type assigned to the transistor P of the PMOS type and whose ports are interconnected with the same terminal S4 represents a capacitor C against the terminal S2 on the contact to which the drain electrode of the transistor P and the source electrode of the transistor N are connected.

In this way, under the condition that the capacitor C is positively charged at the terminal connected to the two gates of the transistors P and N with respect to terminal S2, and that on the other hand the voltage on terminal Sl is more positive than the which is present on S2, the transistor N conducts, which makes it possible for a current to flow from terminal Sl towards terminal S2 through transistor Tl due to the fact that transistor N with its drain/source path short-circuits the base electrode of transistor Tl, which this drain electrode is connected to, while the emitter of Tl is connected to Sl. The effect of this conductivity of Tl is to pump current into the base electrode of transistor T2, which is directly connected to the collector of Tl in such a way that T2, which is of the NPN type, begins to pump current into the base electrode of Tl, which is directly connected to the collector of T2,I.whose emitter electrode is directly connected to S2. In this way, by this cumulative effect, the two transistors T1 and T2 will be placed in a saturation state which offers a low impedance between S1 and S2. The transistor T3 is of the PNP type, like Tl, and the base electrode and the emitter electrode of these two transistors are interconnected, while the collector of T3 is at the same potential as S2, and thus also becomes conductive, but, as indicated, this concerns a parasitic element without affecting the main working method of the circuit.

The biased contact S, which exhibits a low resistance between S1 and S2, can now be brought back to its high impedance state v.hj.a. a negative charge on the capacitor C, and this negative potential at the gates of the transistors P and N with respect to S2 now leads to conduction in transistor P which is of the PMOS type. While the transistor N of the NMOS type has its drain electrode connected to the base electrode of Tl, the source electrode of P is connected to the collector electrode of Tl in such a way that P draws current from the collector electrode of Tl so that the base current of T2 becomes insufficient to maintain the conductivity of this NPN transistor, which by a cumulative effect leads to blocking of itself and of Tl and T3, while the thyristor Tl/2 does not become conductive. It will still apply as shown in fig. 1 that the P and N substrates are connected to the N drain electrode and to the P source electrode, respectively.

The second S<1> connector is only shown in the form of a block i

fig. 1, but it operates exactly in the manner described, but this time under the control of a positive or negative charge on the capacitor C and more particularly at its terminal S4 on its terminal S'2. But these operations of the half-contacts S<1> will this time occur when the polarity of the circuit, in which the switches are inserted in antishunt connection, is positive in S'l with a view to

S'2. It should be noted that the realization of S/S' in a single integrated circuit comprises a connection between the common base of the transistors T1 and T3 for the two contacts S and S'. .. As already shown in Belgian Patent No. 896 388, capacitors such as C and C can be constituted by parasitic capacitances, in particular those appearing at the gates of the transistors P and N of the capacitor C. Both C and C can be charged with the desired polarity using the control circuit shown in fig. 2 and essentially corresponds to a version already described in the latter Belgian patent.

In reality, the transistors NA and NB, both of which are of the NMOS type, are shown in fig. 1 with its source electrodes directly connected to terminal S3, while the drain electrodes of NA and NB are respectively connected to Sl and S2. On the other side, the gate electrode of NA will be connected to S2, while the corresponding electrodes for NB are connected to Sl. Such a circuit arrangement means that if the potential of Sl e.g. is higher than that applicable to S2, the potential of S3 will not be able to be outside this range, and the transistors NB and NA become conductive, respectively blocked, which in reality means that the terminal S3 in practice (with a voltage drop of 0.7 V ) is connected to terminal S2, and with reference to fig. 2 it can be seen that the capacitor C is actually connected between the terminals S4 and S3 of the charging equipment shown in fig. 2. The parasitic diodes between the source electrode and the drain electrode of the transistors NA and NB, i.e. DA and DB as shown in fig. 1, are biased in such a way that they play analogous roles by setting terminal S3 in readiness to bring itself and the potential of terminal S2 when the latter is less positive than terminal Sl.

Of course, according to symmetry considerations on the circuit comprising the transistors NA and NB, the states will be inverted when the potential of S2 is higher than that present on Sl, and as a result of this and the conductivity of NA or DA will clamp S3 this time in practice connect to terminal S'2 in such a way that in these cases it is the capacitor C that is effectively connected to the input terminals S4 and S3 of the control circuit in fig. 2.

In this way, a single control circuit can automatically close or open the half electronic contact S or S<1>, depending on the polarity of the voltage supplied between the terminals Sl/S<1>2 on the one hand, and S'2/S' l on the other hand.

As already shown, the circuit in fig. 2 essentially described in Belgian patent no. 896 388 and particularly in connection with fig. 6 of this patent, which is very similar to fig. 2 in the present application. The latter circuit comprises an AC/DC converter in the form of a full-wave cascaded voltage doubler and fed in push-pull by clock pulses with complementary polarity. The polarity control of the circuit in fig. 2 is effected by means of the signal DC supplied to series capacitance C3, while the complementary clock signals CL and CL are permanently supplied to the two other series input capacitances Cl and respectively. C2. In the same way as for the output capacitance

C/C (fig. 1), which exists between terminals S4 and S2/S'2, is

these three input capacitances are not necessarily made up of discrete physical elements. The first voltage doubler-like-

dishes are mainly composed of series capacitance Cl, followed by series diode Dl, transistor Pl of PMOS type to reach shunt capacitance C/C between terminals S4 and S3, the shunt diode of this voltage doubler is D2 connected as shown between the connection point

to Cl and Dl on the one hand and the connection point between C3 and port Pl on the other hand. When the control potential DC, applied to series capacitance C3, corresponds to the clock pulses CL applied to series capacitance C2, it is the described charging circuit which effectively ensures a charging of capacitor C/C in such a way that the potential at terminal S4 will become more positive than that at terminal S3.

In the inverse case, when the control signal DC, which is applied to series capacitance C3, corresponds to the clock pulse CL which is permanently applied to series capacitance Cl, the output capacitance C/C will this time be charged with S4, which is more negative than S3, and the elements of this voltage doubler will reach act so that the shunted output capacitor is charged negatively and consists of C2, D3, Ni and D4, which respectively correspond to Cl, D1, P1 and D2, as shown in fig. 2, and where transistor NI is of the NMOS type.

As shown in Belgian patent no. 896 388, the positive charging circuit which makes use of the charging capacity of transistor P1 is completed by transistor N2 of the NMOS type, whose drain electrode is connected to S3, and whose source electrode is connected to the condenser

tor C2 by means of series diode D5, as the gate electrode of N2 is connected to S4. This connection thus allows a completion of the return circuit for the positive charge by providing a path

between "earth" output terminal S3 and input "earth" terminal, which is constituted by the right electrode of series capacitor C2. In the same way, at a negative charge of the output capacitance between S4

and S3, the return road this time will be completed v.hj.a. transistor P2 of the PMOS type in series with diode D6, and these two elements then correspond to N2 or D5, as shown by the circuit which is practically identical to that in fig. 6 and is shown in Belgian patent no. 896 388, except for the diodes D1 and D3, which this time are found on the source side of the transistors P1 and NI instead of being placed on the

since as in the previously known patent. Another version of this circuit is shown in; fig. 4 of this earlier patent, where the diodes D1 and D3 are already placed on the source side of the transistors P1 and N1, but in this circuit the gates of the transistors P2 and N2 were interconnected by another circuit and not connected to the drain electrodes of the transistors P1 and N1 ( S4),.in such a way

that diodes D5 and D6 were this time on the drain side of transistors N2 and P2. In this version of fig. 2 on the other hand is the four. diodes, D1, D3, D5 and D6 all located on the source side of the transistors to which they are assigned in such a way that with diodes D2, D4 and D10, they are all arranged on the side of the three input capacitors Cl/2/3. This last diode D10 directly connects the capacitors Cl and C3 in the same way as in the previous patent, and the Zener diodes D7, D8 respectively. D9 in parallel with the output terminals S4/3, and the source/drain path of transistors N2 and P2 are also connected in the same way as before.

The integrated circuit IC, which may comprise 8 electronic contacts of the type shown in fig. 1, as well as 8 control circuits of the type shown in fig. 2, appears in the form of a block in fig. 3, and this essentially corresponds to a part of fig. 1 in the Belgian patent no. 896 468 and can be used as a line circuit for an electronic telephone system. As shown in fig. 3, a subscriber line (not shown) can be terminated at terminals LT1 and LT2, preferably through a surge protection circuit, e.g. of that type

which is shown in Belgian Patent No. 896 468. By means of the first electronic contact Sil forming part of the integrated circuit IC, terminal LT1 can be connected to series resistance RI and then by means of a second series contact of electronic type, e.g. e.g. S21, to the SLIC circuit which contains other elements of the electronic line circuit. The circuit between the second input terminal LT2 and the SLIC circuit is exactly the same, and S12, R2, S22 correspond to Sli, RI, respectively. P21. In addition to the series contacts that make it possible to connect the resistors between LT1/2 and the SLIC circuit, these resistors can also be connected via four shunt contacts to the test circuits TC (S31 for Ri and S32 for R2) on the subscriber side (LTl/2)

on the one hand and towards the ring circuit RC (S41 for RI and S42 for R2) on the central side (SLIC) on the other hand. Connections that are not shown in the figure and that lead from the terminals to the

the positions Rl/2 of the SLIC, enable the latter to monitor the potentials arising across these resistors.

The operation of the eight contacts is controlled from the SLIC through the four conductors that terminate at the terminals Ici/2/3/4'°^the contacts of a pair such as S^^y^ are controlled by the same signals so that the two wires of the connection are switched simultaneous. However, the fourth conductor reaching IC4 is indicated by broken lines, as this control can be effected in accordance with a control mode using only three binary signals, a mode selecting signal applied to terminal IC5 which determines whether three or four binary signals is used to control the four contact pairs Sll/12, S21/22, S31/32 and S41/42.

This versatility of the IC circuit is based on that fact

that the placement of these four pairs of contacts, directly on either side of the resistors RI and R2, makes it possible to ensure adequate control with a number of connection states not exceeding eight. Consequently, when the four contact pairs of the circuits IC are used for any application, line circuit or otherwise, the need is between 9 and 16 possible states for the combination of these four pairs in their open and closed states, and each of the four binary signals at the terminals Ici/2/3/4^an ^i^-^e control the state of a pair of contacts. On the other hand, particularly in the case of telecommunication line circuits which will be described in more detail below, one can be satisfied with a maximum of eight states, and the selection signal at terminal IC5 will this time indicate that only three binary signals at terminals Ici/2/3/ 4 can be taken into account, and the eight possible combinations of these signals will be transferred using a decoder DEC to four binary signals, each of which can control a pair of contacts.

This is shown in the form of a block in fig. 4 which represents the elements that make up the circuit IC in fig. 3, apart from the electronic contacts and their control circuits for capacitor charging as already described in connection with the figures 1

respectively 2.

In fig. 4, each of the inputs Ici/2/3/4/5<k>oblet t;L1 is the input of a corresponding inverting circuit Ivi/2/3/4/5 and apart from the case of IC5, where the connection is direct, the connection is made through indent protection circuits<p>ci/2/3/4'

and the circuit PCI is described in detail in fig. 5.

This latter figure shows that the input terminal ICI is directly connected to the output terminal A, and the input binary code of IC is identified by ABCD, and the output terminals B, C, D, which respectively correspond to the terminals IC2/3/4*Input terminal ICI is connected to the poles VI and V2 ti!:a direct voltage source through the diodes D11 and D12 respectively, these.limit the potential on ICI/A, and between these, VI and V2, the last potential, e.g. 0 Volts, which is more negative than VI, 15:Volts. On the other hand, transistor P3 of the PMOS type has its source electrode connected to VI, its drain electrode to A and its gate electrode to V2 in such a way that it is continuously kept conductive. Transistor T4, which is shown with broken lines, as it is of the NPN type and has its collector electrode connected to ICI and its emitter electrode to V2, can be used to bring a binary control signal to ICI. If its base electrode is at the potential VI, it is conductive, and it becomes possible for the current to pass from VI to V2 through the series connection of P3 and T4. The impedance of the latter transistor is smaller than that of P3, and therefore terminal A is at potential V2. On the other hand, if the base electrode of T4 is at the potential of V2, so that T4 is blocked, terminal A will be at the potential of VI transmitted through P3.

Fig. 4 shows that the four potentials (ABCD) at the outputs of PCi/2/3/4 t:i-lf are brought to the terminals such as D to the gate electrode GD through inverting circuits such as IV4, in such a way that a complementary binary code ABCD appears at the inputs to these ports (ports identical to GT are provided for the signals at terminals A, B, and C) with respect to the binary code ABCD at the outputs of PCI/2/3/4. Three of these binary signals ABC

is, on the other hand, supplied to the decoder DEC together with the two signals A and B which are complementary to A and B and are obtained by the inverting circuits IV6 and IV7 connected in cascade with IV1 respectively. IV2.

Before it is explained with the help of Figures 9 and 10 how the decoder DEC can transform the eight combinations of three binary signals ABC into special combinations of four binary signals at its outputs E F G" H, the description of the other elements in Fig. 4 will be completed, as it begins with the above-mentioned port GD, the output of which is connected to the output of an identical port GH

ID

which is fed by the H output from the decoder DEC, as three identical ports (not shown in the figure) are used and connected in the same way to the outputs E F G.

Ports such as GD and GH are controlled from terminals IC5 which determine the operating method of the IC with or without decoding by DEC, and the binary signal to IC5 - is supplied to all ports such as GD/BH as well as the complementary binary signals. ■ which is obtained from inverting circuit IV5.

Figure 6 shows the circuit of a transmission gate such as GD and GH, which connects input terminal D or H to output terminal DH

at the source/drain path to the transistors N3 and P4 connected in anti-shunt coupling and which are NMOS or PMOS type. Their gate electrodes are connected to IV5 or IC5 for GD and vice versa for GH in such a way that one of these ports is conducting and the other is blocked depending on the selector signal of IC5, which allows such terminals as DH to either select signal D and parts of a four-element binary code each identifying a pair of contacts such as S11/12 (Fig. 3), or the signal H, i.e. one of the four binary elements decoded from DEC from the three binary elements ABC.

As shown in fig. 4, the signals at the terminal such as DH must still be synchronized by the gate such as GC with clock pulses provided by oscillator CO, and these must be fed together with the complementary clock signals CL and CL to the three input capacitances C]y2/3 from AC/DC push-pull the converter, (fig. 2) , which serves to charge the capacitances C/C<1> in the positive or negative direction and controls the biased electronic contacts S/S', which are connected in antishunt connection (fig. 1). Fig. 7 shows the circuit of the clock gate. The binary signal at the terminal such as DH, which determines the open or closed state of the corresponding contact, is this time supplied to the control ports GCA and GCB which are identical to those shown in fig. 6, except for the inputs which are supplied with the complementary clock pulses CL and CL used by the oscillator CO. The gates GCA and GCB are controlled in a complementary way by the signal DH and its complement is produced by the inverting circuit IVg in such a way that the output signal DC from the gate GC is either a CL pulse or a complementary CL pulse in accordance with the value of the binary signal in DH. Fig. 8 shows the clock oscillator CO, which comprises the three inverting circuits iviq/11/12<k>obled in cascade in a loop which also comprises the series resistances R3 and R4 on each side of the inverting circuit and the output from °9 which feeds another series consisting of of three inverting circuits ^ i^/ lA/ lb in cascade and the last of which provides the clock pulses CL and the complementary pulses CL. Oscillator CO is also fed by the voltages V2 (not shown) and VI, and the ..last of these is connected to the inputs of Ivi]_/i2/13 through the respective capacitances £4/5/5*These can be of 6 picofarad and Ro/4 of 20 kohm to produce oscillations at a frequency of the order of 1.2 MHz.

As shown by the multiple arrows in fig. 4, feeds the oscillator

CO the four ports such as GC, whose output terminals control two charging circuits such as those shown in fig. 2, for controlling a pair of contacts such as those shown in fig. 1. This last connection is carried out by inverting circuit IVg, which provides sig-

naled DC in such a way that the three signals arrive at the capacitances C^/2/3*~ f i(3' 2 through the output impedance of an inverting circuit.

The decoder DEC in fig. 4 will finally be described with reference also to figures 9 and 10, which represent the logic circuit types which are advantageous for use in realizing this circuit.

In order to achieve this, one will first of all define the eight states by which a telephone line circuit can be characterized, given a combination of the input signals ADC to the decoder DEC.

These eight states are identified by the truth table as follows:

The table comprises three columns corresponding to the input signals ABC, a fourth column for an intermediate signal Y, the applicability of which will appear later, and four further columns E F G H which define the signals at the output of the decoder DEC, and each

.of these last columns correspond, as indicated, to the condition of a pair of contacts, e.g. E for sn/±2'

The complementary line at the top of the references identifies the contacts corresponding to the complementary form of E F G H on a. such that the indication 0 identifies a closed contact for the slots in question, while 1 represents an open contact. The eight states for the line circuit then appear in the form of successive rows in increasing order for the binary code from 000 to 111 for ABC, and this last code corresponds to the through-connection of the line circuit in fig. 3, i.e. the series contacts S11/120<^ S21/22 are closed, and the shunted contacts S21/ 32 °^ S41/42 are ^Pne* The fourth<3e line gives the code 011 for ABC as the ring state, and enables the connection of RC (fig 3) in the direction of the terminals LT^y2 to the subscriber line through the resistors R-^/t in such a way that the voltages on the latter can also be used for monitoring the ringing operation for the called subscriber.

The sixth line corresponds to code 101 for ABC and an internal test

(in the direction towards the switchboard) and this time enables the test bus TC to be connected to the SLIC through the resistors Rl/2. On the other hand, the external test (in the direction of the subscriber) on the fifth line (100 for ABC) will produce a connection between TC and terminal LT^/2without * passing through the resistors while ring test (001 for ABC) this time connects RC and TC through the resistors.

Apart from these five states, the line circuit still enables a complete isolation of the resistors (000 for ABC), where TC is also branched off with S21/ 32^a ^a above-mentioned output connection, and finally a monitoring state (110 for ABC), where TC is also branches off, but this time from the normal connection.

The eight codes ABC, which enable these different states, have been assigned to each of the eight contact combinations ^ W/\ 2' ^21/22' ^31/32' ^41/42' as indicated in the table, and this enables the simplest possible realization of DEC. In reality, the corresponding table indicates that E = B and that F = A except for ABC = 100, and that G = 0 except for ABC = 000 and BC = 11, and finally that H = A except for ABC = 000. The realization of the decoder DEC is simplified by these simple correspondences and by the introduction of Y = 0 except for BC = 00, Y being an internal binary signal appearing at the fourth column of the table.

According to the above, one can write the corresponding Boolean equations:

where the second expression for E (fig. 9) will simplify a comparison with G (fig. 10) and those that apply to F, G and H are obtained by replacing Y with the value shown which for Y more directly corresponds to the logic circuits which is used and more precisely is a derivation of what applies in fig. 10 for G.

Fig. 9 represents the CMOS logic that makes it possible to realize E by using three PMOS transistors connected as shown between potential VI and the output terminal that provides the function E, as well as three NMOS transistors connected as shown between the output terminal and potential V2. These three transistors are identified by the signals A, B, C and are supplied to their gates, both for the PMOS and for the NMOS transistors. Their source/drain paths are connected to each other in such a way that B is in series with a parallel combination AC for the PMOS transistors, while the duality of the circuit comprising the NMOS transistors means that B must be in parallel with the series combination A C. Therefore, since the signals A, B, C are respectively the complement of the signals included in the equation that gives the value of E, one will especially see that if B is at the low potential, transistor B among the PMOS transistors will be conducting, while the corresponding NMOS transistor is blocked. If one forgets transistors A and C among the PMOS transistors by replacing them with a short circuit, due to the duality of the circuit, one will see that the NMOS transistors A and C are replaced by an open circuit, E will then be at a high potential (VI), which corresponds to E = B, and this latter value is then the first factor in the expression which defines E and represents a condition which, like what was previously shown, is true for all combinations" of ABC, except 100. But for this last combination with A and C at high potential and B at low potential, the PMOS transistors are controlled by A and C,.and both are therefore blocked while both the corresponding NMOS transistors are conducting. For this particular combination. ér; therefore E at lower potential (V2), which corresponds to E = B. For seventy other combinations, the four transistors A and C (PMOS and .NMOS) will be irrelevant because they can neither short-circuit the blocked transistor B (NMOS) nor set it conducting B transistor (PM OS) as an open circuit in such a way that only B remains relevant and that E = B.

Fig. 10 represents the circuit capable of realizing the function G according to similar principles as those which have been described for fig. 9, as the second form given above for E enables a direct comparison with the first value applicable to G. In reality it is easily seen that there are four independent variables A, B, C and Y for G as opposed to only three (A, B and C) for E. In this way, four pairs of PMOS and NMOS transistors are connected as shown, and they are all needed this time and act on the temporary variable Y.

To obtain the value of the latter from B and C, as well as F and H from A and Y, and from A respectively Y, it is sufficient each time to take half the circuit in fig. 10, e.g. transistors B and C, both for the series connection of the PMOS transistors and for the shunt connection of the NMOS transistors by allowing these to be controlled by suitable signals, e.g. of B instead of B, and C instead of C to produce Y.

In this way, the entire decoder DEC, which only requires the five signals A, A, B, B and C by economizing an inverting circuit for C (fig. 4), can use only 13 PMOS transistors and 13 NMOS transistors.

Reference is now made to fig. 11 which shows the electronic contact Sil in fig. 3 in more detail, and this contact is a modification of that shown in fig. 1. While it is still of the TRIMOS type, the thyristor TRX which is formed between terminals Sl and S2 deviates slightly from the one schematically shown in fig. 1 in that PNP transistor Tl is now replaced by PNP transistor Ql with two distinct collector electrodes which are respectively connected to the gate electrodes of two NPN transistors Q2 or Q3 which replaces NPN transistor T2, since transistor T3 is not shown. Furthermore, individual protection circuits for the power supply are described, and these are described in more detail below in connection with the TRX.

It should be noted that contact S12 is identical to Sil, but that the other six contacts do not include protection circuits for the power supply. The electronic contact Sil in fig. 11 comprises two identical switching circuits -.-S and S' which are connected in an anti-shunt connection. More specifically, the terminal S1 to S is connected to the terminal S'2 to S', while the terminal S2 to S is connected to the terminal S'1 to S'. The control circuit mentioned above is connected to both S and S' across terminal S4. The switching circuits S and S' are also each provided with a detecting output terminal DT1, DT2, of which only DT1 is connected to a fault indication circuit FC via detecting terminal DET1. FC is also included in the integrated circuit IC and will be described below. Because S and S<1> are identical, only one of them will be described below.

As already mentioned above, the transistor Qi of the thyristor TRX has two distinct collector electrodes which are connected to the base electrodes of the transistors Q2 or Q3. The collector electrodes of transistors Q2 and Q3 are both connected to the base electrode of Q1. Terminal S1 is connected to the emitter electrode of Q1, and terminal S2 is connected to the emitter electrode of Q3 directly and to the emitter electrode of Q3 indirectly via a sensing resistor R1. The base electrode of Q2 is also connected to the collector electrode of an NPN transistor Q4, whose emitter is connected to terminal S2. The terminal Sl is connected to the base electrode of Q4 via the cascade connection of a diode D21, the collector-emitter path of the NPN transistor Q5 and a resistor R12. The cathode of diode D21 is also connected to the emitter electrode of Q3 via the series connection of a resistor R13, the source-drain path of an NMOS transistor Nil and a resistor R14. The connection point between resistor R14 and the source electrode of Nil is connected to the base electrode of an NPN transistor Q6, whose collector electrode is connected to the base electrode of Q3, and whose emitter electrode is connected to terminal S2. The cathode of diode D21 is also connected to the drain electrode of an NMOS transistor N12, the source electrode of which is connected to the base electrode of Q5 together with the detection output terminal DT1. The gate electrodes of Nil and N12 are both connected to the drain electrode of DMOS transistor .N13 with its source electrode connected to terminal S4 and its gate electrode connected to terminal S2. It should be noted that DMOS transistor N13 has a parasitic diode (not shown in the figure), whose anode is connected to the source electrode of N13, and whose cathode is connected to the drain electrode of this transistor, and that NMOS transistors Nil and N12 have high gate capacitances ( not shown).

The thyristor TRX is switched on and off by means of MOS transistors (not shown) corresponding to transistors P and N.i. fig. 1, and is controlled via terminal S4. As already mentioned above, switching circuit S includes protection circuits for the power supply, and these are also able to control the TRX, the operation of which will be described in detail below.

The thyristor TRX is assigned to two distinct power supply protection circuits, called primary and secondary protection circuits. The primary protection circuit for the power supply comprises components D21, N12, Q5, R12 and Q4, and specifically limits the current through TRX when the voltage across circuit S exceeds a predetermined value. The secondary protection circuit for the power supply comprises components D21, R13, Nil, Q6, R14 and Ril. It should be noted that in the following description of the operation of the protection circuits it is assumed that the voltage at terminal Sl is positive with respect to the voltage at terminal S2, so that diode D21 is forward biased. The same function is valid for S' if the voltage S'2 is positive in relation to the voltage at S'1.

The primary and secondary protection circuits are put into operation and switched off using the NMOS transistors Nil and N12, which itself is controlled by DMOS transistor N13. When the thyristor TRX is in its on state, a positive control voltage of approx. +2OV is fed to terminal S4 and is transferred to the gate electrodes of Nil and N12 across the parasitic diode of transistor N13. As a result of this, transistors Nil and N12 will become conductive, and the protection circuits are operational. To switch off the thyristor TRX, the control voltage at S4 is reduced from its positive value of approx. +20V to a negative value of approx. -20V. During this voltage shift, the TRX is switched off when the voltage at S4 reaches approx. -3V, while the protection circuit remains in operation when the parasitic diode of the DMOS transistor N13 is blocked. In reality, the NMOS transistors then remain conductive due to the positive voltage held by their gate capacitance. When the voltage at S4 reaches approx. -8V; transistor N13 becomes conductive so that this negative control voltage is supplied to the gate electrodes of Nil and N12 and blocks them: The protection circuits for the power supply are then out of service. Transistor N13 is connected to the gate capacitance of transistors Nil and N12 and thus constitutes a delay circuit which brings the protection circuits out of service for a time interval after the blocking of TRX. Thus, the protection of this equipment will remain in operation as long as the TRX is in its on state.

When the TRX is in its on state, no current will flow through the primary protection circuit as long as the voltage across the switching circuit S does not exceed a voltage drop corresponding to the voltage across approx. three diodes. These three diodes are diodes D21, the base-emitter path of transistor Q5 and the base-emitter path of Q4. It should be noted that the current flowing through the primary power supply protection circuit is so small that the voltage drop across the resistor R12 is negligible, while the voltage drop across the drain-source paths of the conducting transistor N12 is also negligible, because the latter voltage drop is proportional to the base current of the transistor Q5, which is still blocked. As the voltage across S increases, transistor Q4 will become conductive, and the collector current of Ql will be drained from the base electrode of Q2 to terminal S2. As the base current of transistor Q2 is reduced, its collector current, and consequently the base current of transistor Q1, will also be reduced. As a result, the part of the thyristor TRX corresponding to the transistors Q1/Q2 will be turned off, while the part corresponding to the transistors Q1/Q3 will remain turned on as described below.

During the above operation, the main current in transistor Q4 will be limited by resistor R12 and transistor Q5, which itself is controlled by transistor N12.

If one now only considers the part Q1/Q2 of the thyristor TRX, the current-voltage characteristic of the switching circuit S will be that shown in fig. 12, where part 1 is the normal current-voltage

characteristic of the forward-biased thyristor TRX.

As shown, the voltage V rises to the maximum voltage Vp, which is equal to the above voltage drops for three diodes (±2.1 V) and corresponds to a maximum current 1^ of 320 milliamps. From the above it follows that the transistor Q4 becomes active at the maximum voltage V"D which corresponds to the current 1^ so that TRX turns off .• ■] and follows the part 2 to the -current-voltage characteristic shown in Fig. 12. -The current in the thyristor TRX and therefore also in the switching circuit S is then practically equal to zero regardless of what the voltage across the circuit may be, so that the current-voltage characteristic closely coincides with the voltage axis for voltages that exceed V"D. It should be noted that this current-voltage characteristic is valid for thyristor TRX as well as for switching circuit S.

The DC load line 3 of the switching equipment S is also shown in the diagram in fig. 12. It is defined by two points corresponding respectively to the maximum current IL (70 milliamps) in the telecommunications line when the latter is short-circuited and the maximum voltage VT(70 Volts) when the line is open. This DC load line 3 crosses part 1 of the current-voltage characteristic of the switching circuit S at a stable operating point 4.

When unwanted abnormal signals are supplied to the telecommunications line, these are added to the normal signals generated by the telecommunications exchange, so that the load line moves in the current-voltage diagram shown in fig. 12. Such abnormal signals can have different origins, e.g. lightning strike in the telecommunication line or an incorrect interconnection of power supply lines and communication lines due to damage or failure. The operating point will then move along part 1 of the current-voltage characteristic. When such unwanted and abnormal signals become very large, the load line can be shifted in such a way that the operating point reaches the upper part 1 of the current-voltage characteristic. This operating point then becomes unstable and moves towards higher voltages while the TRX is switched off (part 2). However, the maximum voltage VM across switching circuit S will be limited to approx. 250 V due to the overvoltage protection (not shown) mentioned above, so that the operating point will then be at the point VM on the voltage axis.

When the abnormal signals disappear, the DC load line is shifted back to the position drawn in fig. 12, and the operating point moves from VM (250 V) to VT(70 V), where

'M 1j

the part of the current-voltage characteristic of the TRX that coincides with the voltage axis crosses the DC load line 3. The operating point thus becomes stable at this voltage V , and because the primary protection circuit for the power supply is then still active, it is impossible to strike the thyristor TRX on. To allow TRX to be turned on again, the part 2 and the part of a current-voltage characteristic of the switching circuit S which coincides with the voltage axis must not cross the DC load line 3, so that no stable operating point such as VL exists between V r. i, and the normal operating point 4. A solution is to use the secondary protection circuit for the power supply, which circuit is described below.

Now let's look at this secondary protection circuit for the power supply. When the switching circuit S is in its on state, a current flows from Sl to S2 (Fig. 11) not only via TRX, but also via diode D21, resistor R13, the turn-source path of NMOS transistor Nil and resistors R14 and Ril in series. As long as the voltage between terminals S1 and S2 is relatively small enough that the voltage drop produced by the above currents across R11 and R14 in series is less than the base-emitter saturation voltage Vn_ to Q6, the latter will remain blocked. The current I, which flows through TRX, then varies as a function of the voltage V measured across the switching circuit S according to part 5 to the current-voltage characteristic shown in fig. 13. It should be noted that due to the values of the resistors (these will be given later) the current I (Fig. 11) flowing through the TRX is much greater than the current flowing through the secondary protection circuit. Therefore, the current I can be considered to be the current flowing through the switching circuit S and, in the same way as for fig. 12 applies to the current-voltage characteristic in fig. 13 both for the thyristor TRX and for the switching circuit S. When the voltage between the terminals between Sl and S2 is so great that the voltage drop produced across Ril and R14 in series, by the above currents, becomes greater than the VBE of Q6, the latter becomes conductive and forms thereby a shunt path to Sl for the collector current of Ql. Thus the base current of Q3 will be reduced, and as a result the impedance of TRX will increase so that the current I flowing through it varies as a function of V in the manner shown at section 6 of the current-voltage characteristic in fig. 13. This variation is a function of the power loss in TRX, because the voltage drop developed across the switching circuit S depends not only on I, because Ril is connected in series with TRX,>: mén also of V, since an additional current which is a function of V, "' f flows- -through Ril via R13 and R14. Without R13 and R14, the current I would remain constant and would be equal to the maximum current I2 as shown by. part 7 of the current-voltage characteristic of Fig. 13. In that case, the power consumption in the switching circuit S becomes very large, since part 7 crosses the line of maximum power loss 8 in the circuit S. For reasons mentioned above, part 6 of the current-voltage characteristic should not cross the DC load line 3. On the other hand, because the minimum power consumption in the switching circuit occurs at the operating point of this circuit, i.e. at the crossing point between part 5 of the current-voltage characteristic and the DC load line 3, part 6 of the current-voltage characteristic is chosen as close as mu equal to the direct-voltage load line 3 in order to achieve a minimum of power consumption in the switching circuit S. Therefore, the slope of part 6 of the current-voltage characteristic is chosen equal to the slope of the direct-voltage load line 3. This slope is a function of the ratio R3/R4. In reality, when Q6 begins to conduct, its base-emitter saturation voltage V_.„ can be defined by the following expression: Here V and I are respectively the voltage across and the current flowing through the switching circuit S. This expression immediately leads to

according to the values of the resistors that are

R^<=>7.6ohm

R12= 500 ohms

R^2= 145 kilo-ohms

<R>14<=>1 kilo-ohm.

The following assumptions can be made

and the final expression is such that

From this expression it is clear that the current I is off-RI 4

depending on the voltage -^j-j .V.

Since part 6 of the current-voltage characteristic is chosen as close as possible to the DC load line 3 to limit the power loss in the switching circuit S, the maximum current I2 must be selected slightly higher than 1^, and the maximum voltage V2 must be selected slightly above VT. In the present example and with the values of the resistors given above, I2 equals 100 milliamps, and V"2 equals 100 Volts with approximate values. However, according to requirements and standards conventional for telecommunication systems, the protection circuit should only is activated for a current that exceeds 300 milliamps. If I2 is therefore chosen higher than the required 300 milliamps, part 6 of the characteristic should be shifted upwards, and part of it can be placed above the line of the maximum power loss 8. In this in this case, when the power supply protection circuit becomes active, the power loss in S will be so great that the latter will be destroyed.

The disadvantages of using two separate power protection circuits can be eliminated by combining these two circuits, and this combination gives the overall current-voltage characteristic of the switching circuit S as shown in fig. 14. This characteristic has part 1 and part 2 corresponding to the current-voltage characteristic of the primary protection circuit for power supply, and part 6 to the current-voltage characteristic related to the secondary protection circuit. From this figure it is clear that the current-voltage characteristic crosses the above-mentioned direct voltage load line 3 at a particularly stable operating point 4, and that the power consumption in the switching circuit S is reduced to its minimum, because part 6 is very close to the direct voltage

load line 3.

A fault indication circuit FC is shown in fig. 15. FC has input terminals DETl; and DET2, terminals LT1 and LT2, output terminal FO

and power supply terminals VDD(-33 Volt) and Vgs(-48 Volt) . The fault indication circuit FC is only associated with the protection circuit S of the switching unit S1 (Fig. 11) and to the corresponding protection circuit in the switching unit S12 (not shown). This is sufficient to detect abnormal signals of any polarity on the telecommunication line loop that forms the connection between LT1 and LT2.

The input terminal DET1 of FC is connected to the detecting output terminal of the same name in the protection circuit S of the switching unit Sil (Fig. 11), while the input terminal DET2 of FC is connected to the detecting output terminal of the protection circuit corresponding to S in the switching unit S12 (not shown) . The terminals LT1 and LT2 of the fault indication circuit FC are respectively connected to the line terminals of the same name in the subscriber line. The output terminal FQ of the fault indication circuit FC is connected to a digital signal processor or DSP circuit (not shown), which also forms part of the telecommunications line circuit.

The fault indication circuit FC comprises an NPN transistor Q7,

whose base electrode is connected to input terminal DET.1 across a resistor R15, and whose emitter electrode is connected to terminal LTl. The supply terminal VDDer connected to the collector electrode of Q7 across resistor R17 and diode D22, which are connected in series. Another NPN transistor Q8 has its base electrode connected to the input terminal DET2 across a resistor Ri6 and its emitter electrode connected to terminal LT2, while the connection point between resistor R17 and diode D22 is connected to the collector electrode of Q8 via diode D23. This connection point is also connected to the gate electrodes of an NMOS transistor N14 and to a PMOS transistor Pil, the source electrode of Pil being connected to VDD, and the source electrode N14 being connected to Vsg. The drain electrodes of Pil and N14 are both connected to the gate electrode of an NMOS transistor N15, the source electrode of which is connected to Vgs over a resistor R18. The output terminal FQ is directly connected to the drain electrode of transistor N15.

The fault indication circuit FC works as follows: When no abnormal signals are detected by the power supply protection circuit for the switching circuits S in Sil and S12, or when these protection circuits are put out of service, the voltage at the input terminals DET1 and DET2 does not become sufficiently positive for the purpose of the respective terminals LT1 and LT2 to make their respective transistors Q7 and Q8 conductive. Then no current flows through the diodes D22 and D23 and consequently also not through resistor R17, so that the voltage (V^. "' x.i,j.cV x DD) which is supplied to the gate electrode N14 becomes more positive than the voltage (Vss) at^its source electrode. -Transistor N14 therefore becomes conductive, while transistor Pil is blocked, since it has the same voltage (VDD) at its source and gate electrodes. As a result, transistor N15 is also blocked, and no signal is transmitted to the output terminal Fq. Alternatively, when an abnormal signal is detected by the power supply protection circuit for a switching circuit S, a voltage positive with respect to the voltage present at terminal LT1 (LT2) will appear at the input terminal DET1 (DET2) of FC. It it should be noted that the voltage at terminal LT1 (LT2) is more negative than the voltage at terminal V"DD. Transistor Q7 (Q8) then becomes conductive, and a current can flow from VDD to LT1 (LT2) via resistor R17, diode D22 (D23) and the collector-emitter path of transistor Q7 (Q8). As a result of this, transistor N14 is blocked, while transistor P1 becomes conductive, so that the voltage VDD appears at the gate electrode of transistor NI5, which also becomes conductive. The circuit N15/R18 thereby generates a current which is transferred via terminal FQ to the DSP circuit, the latter being able to perform the appropriate operations.

Claims (36)

1. Electronic contact (S/S <1> ) which makes it possible to establish a low or a high impedance between a first (Sl/S'2) and a second terminal (S2/S'l) during control of a circuit (NA/NB) which emits a control signal between a third (S3) and a fourth (S4) terminal, characterized in that two electronic auxiliary contacts are provided which make it possible to establish a low or high impedance between the first and third terminals (NA) and between the second and third terminals (NB), and that the impedance states of these two auxiliary contacts are opposite. 2. Electronic contact according to claim 1, characterized in that it comprises a first biased contact (S), which is capable of providing a low impedance for a predetermined voltage polarity between the first (S1) and the second (S2) terminal, in in parallel with a second biased contact (S <!> ), which is able to provide a low impedance for the opposite polarity. 3. Electronic contact according to claim 2, characterized in that the biased contacts are identical and are connected to each other in an anti-parallel manner (S1/S'2, S2/S'1). 4. Electronic contact according to claim 2, characterized in that the biased contact is of the thyristor type (Tl/2) and comprises two control terminals which enable it to be set to a low or respectively a high impedance state of the control signal. 5. Electronic contact according to claim 4, characterized in that the two control terminals are each connected to the second terminal (S2) by means of a MOS transistor, that the ports with complementary polarities of these transistors are interconnected with the fourth terminal (S4), while the source electrode of one transistor (N) and the drain electrode of the other transistor (P) are interconnected with the other terminal. 6. Electronic equipment (S/S'), which forms part of a circuit that also includes a power source and a load, where the equipment includes aids to limit the power losses in the circuit, characterized in that the power-limiting aids (Ril; R13, R14 ; Q6) are designed so that they will give the equipment a current-voltage characteristic (fig. 13) which starts at the origin, crosses (5) the load line (3) of the equipment and then seeks to follow (6) said load line towards the voltage axis (V2) without again crossing the load line defined by the short-circuit current (IL ) through the equipment and the breakdown voltage (V"L) across it. 7. Electronic equipment according to claim 6, characterized in that it comprises switching equipment (Ql/3) which is capable of establishing a high or a low impedance between the first (Sl/S'2) ... and.other (S2/S'l) terminals defined by means of the current-voltage characteristic. 8. Electronic equipment according to claim 7, characterized in that at least one primary protection circuit for power supply (Ril; R13, R14; Q6) is assigned to the switching equipment (Ql/3) and comprises a first sensing device (Ril) connected in series with the switching equipment, other sensing means (R13, R14) connected in parallel with the switching equipment and regulating equipment (Q6) which is controlled by the first and second sensing equipment and controls the switching equipment so that the aforementioned current-voltage characteristic is achieved. 9. Electronic equipment according to claim 8, characterized in that the first (Ril) and second (R13, R14) sensing equipment are connected in series, and that the control equipment comprises an active component (Q6) with an input part connected across the first sensing equipment and a part of other sensing equipment, and an output part connected to the switching equipment (Ql/3). 10. Electronic equipment according to claim 9, characterized in that the first sensing equipment comprises a resistor (Ril), that the second sensing equipment comprises at least two resistors (R13, R14) connected in series and that the regulating equipment comprises a transistor (Q6). 11. Electronic equipment according to claims 7, 8 or one of claims 1-5, characterized in that the switching equipment (Ql/3) is part of the electronic contact (S/S') and that the protection circuit for power supply (Ril; R13, R14 ; Q6) is connected to cut-down means (Nil, N13), which are controlled by the control signal and are capable of switching the protection circuit on and off after the switching equipment (Ql/3) has reached its high impedance state. 12. Electronic equipment according to claim 6, characterized in that the part (5) of the current-voltage characteristic (Fig. 14) which crosses the load line (3) has a first part (1) which extends, for voltages (V"D) which is relatively much smaller than the voltage that occurs at breakdown (VT ), to a current value (1^ ) which is relatively much larger than the short-circuit current (IL ) and a second part (2) which practically coincides with the first part (1) to,; the. part (6) of the characteristic following the load line (3).. 13. Electronic equipment according to claim 8 or 12, characterized in that it also comprises a secondary protection circuit for power supply (D21, Q5, Rl2rQ4) which comprises a third sensing device (D211, Q5, R12; Q4) to sense the voltage across over the electronic equipment (S/S <1> ) as well as a second regulating equipment (Q4) which is controlled by the third sensing equipment and controls the switching equipment (Ql/3) so that it produces the first (1) and the second (2) part of the current-voltage characteristic. 14. Electronic equipment according to claim 13, characterized in that the third sensing equipment (D21, Q5) R12; Q4) and the second control device (Q4) comprises a first active element (Q4) whose output part is connected to the switching device (Ql/3). 15. Electronic equipment according to claims 7, 13 or one of claims 1-5, characterized in that the switching equipment (Ql/3) is part of the electronic contact (S/S <1> ), and that the secondary protection circuit (D21, Q5, R12; Q4) is connected to the step-down equipment (N12, N13) which is controlled by the control signal and is able to put the secondary protection circuit into operation and out of operation after the switching equipment (Ql/3) has established the high impedance state . 16. Electronic equipment according to claim 7, characterized in that the switching equipment (Ql/3) consists of a second (Ql), a third (Q2) and a fourth (Q3) active equipment, the first output terminals of the third and fourth active equipment being connected to the control terminal of the second active equipment, that the second output terminal of the third and fourth active equipment is connected to the second terminal (S2/S'l), that the first output terminal of the second active equipment is connected to the first terminal (Sl/S'2) and that the second active equipment has two distinct other output terminals which are connected to the control terminals of respectively the third and fourth active equipment. 17. Electronic equipment according to claim 16, characterized in that the second active equipment (Ql) consists of a PNP transistor, whose control, first output and second output terminals are the base, emitter and respectively the collector electrodes, and that the third (Q2) and fourth (Q3) active equipment each consists of an NPN transistor, whose control, first output and second output terminals are the base, collector and emitter electrodes respectively. 18. Electronic switching contact which makes it possible to establish low or high impedance between a first (S1, fig. 11) and a second (S2) terminal on the one side and a third terminal (S3) on the other side, and where the impedance states are complementary for the first and second terminals, characterized in that the polarity of the voltage supplied between the first and second terminals determines the impedance states. 19. Electronic contact according to claim 18, characterized in that the switching contact consists of two transistors of the same polarity, in that the first terminal (Sl) is connected to the first output terminal of the first transistor (NA) and to the control terminal of the second (NB), in that the second terminal (S2) is connected to the first output terminal of the second transistor and to the control terminal of the first, and that the third terminal (S3) is connected to the second output terminal of the transistors. 20. Electronic contact according to claim 19, characterized in that the transistors are of the NMOS type. 21. Electronic switching contact which makes it possible to establish a low or a high impedance between a first (VI, fig. 5) and a second (V2) terminal on the one side and a third (A) terminal on the other side, where the impedance conditions are complementary for the first and the second terminals, characterized in that the first, second and third terminals are connected to the source electrode, the gate electrode and the drain electrode respectively of a MOS transistor (P3) and that the polarity of the voltage supplied between the first and the second clamp is such that it becomes conductive, that furthermore the second and third terminals are also connected to the emitter electrode and respectively the collector electrode of a bipolar transistor (T4) in such a way that when the latter is blocked, a low impedance is obtained between the first and third terminals, while a low impedance is obtained between the second and the third clamp when it is conductive. 22. Controlled capacitive charging circuit comprising' a source with .v push-pull alternating current signals connected to two series input capacitors at the input of a rectifier circuit,• c a r a c t e - r^i'..:s ert in that a third series-connected input capacitor (C3)Hiar its input terminal connected to said source, 6'gl .also has its output terminal connected to the input of the rectifier circuit comprising a first (D1, D2) and a second (D3, D4) part, which are respectively capable of producing either a first or a second direct voltage output signal and in this way make it is possible to charge the output capacitor (C/C) to a first or second polarity by means of control equipment (IC), that the first and the second part of the rectifier circuit are decoupled by the first complementary (MOS) transistors (Pl, NI), whose gates is connected to the third input capacitor (C3) and comprises other MOS transistors (N2, P2) which are mutually complementary to the first, while the two complementary transistors in the first (P1, N2) and the second (NI, P2) part is arranged on both sides of the output capacitor (C/C <1> ), and the other transistors have their gate electrodes connected to the drain electrode of the first transistor with the same polarity, the source electrodes of the two transistors (Pl, P2) with a first polarity (Pl, P2) each connected to the first input capacitor (Cl) of a diode (Dl, D6) and the source electrodes of the two transistors with the second polarity (NI, N2) each connected to the other input capacitor (C2) of a diode (D3, D5). 23. Line circuit for telecommunications systems comprising a series impedance (RI; R2) in each of the two line conductors, as well as contacts (Sil, S31; S21, S41;.S12, S32; S22, S42) on each side of these two impedances which make them capable of selectively connecting their terminals to the switchboard (SLIC) respectively to the line (LTl; LT2) or possibly to auxiliary circuits (TC; RC), characterized in that these contacts are made up of four pairs of electronic contacts, of which the first (Sil, S12 ) connects the line to the impedances, and the others (S21, S22) connect these to the switchboard, while the third contacts (S31, S32) connect the impedances on the line side to a first auxiliary circuit (TC) and the fourth contact (S41, S42) connects them with the central side of a second auxiliary circuit (RC). 24. Line circuit according to claim 23, characterized .in that the eight electronic contacts, which are always operated in pairs, are also controlled in such a way that only 8 combinations of the 16 possible are allowed for the four pairs;.' 25. Line circuit according to claim 24, characterized in that the 8 closed and open combinations result in four pairs of contacts are defined by the 8 binary codes lill, 1100.,. 01.00, 0110,, 0101, 1001, 0001 and 0011, where the first, second, third and fourth digits from the left respectively correspond to the first (Sli/]2), second (S21/22), third (S31/32) and fourth (S41/42) contact pair, while the digits 0 and 1 indicate whether the respective contact is closed or open. 26. Line circuit comprising several electronic contacts capable of being operated in accordance with different combinations by means of binary control signals, characterized by the decoder (DEC) included in the circuit and capable of being controlled by at least part of the signals (IC, -0/0) to provide binary output signals to an arrangement of gates GH) which also directly (GD) receive the binary control signals a selection signal (IC5) which makes it possible to control the gates in such a way that they respectively authorizes and blocks the flow of control and output signals or vice versa. 27. Line circuit according to claim 25 or 26, characterized in that the eight binary input signals (ABC) 000, 001, 010, 011, 100, 101, 110 and 111 which control (IC-L/2/3) the decoder (DEC), corresponds to each of the eight combinations of binary output signals (E, F, G, H) which are the binary signals lil, 1100, 0100, 0110, 0101, 1001, 0001 and 0011 provided by the decoder. 28. Line circuit according to claim 27, characterized in that the binary codes from. the decoder's output is obtained as a function of the binary codes at the input from five logic circuits which are respectively defined by the following Boolean equations where Y is a temporary signal and where A, B and Y are complementary values of each of the values A, B and Y . 29. Line circuit according to claim 26, characterized in that the gate arrangement (GH/GD) provides an output signal that controls the two clock gates in opposite positions in such a way that either one or the other transmits a clock signal or its complementary value. 30. Line circuit according to claim 29, characterized by e-d that the clock signal and its complementary signal. is produced by a clock oscillator which is part of the same integrated circuit as the gate arrangement, the decoder, the electronic contacts and their control circuits. 31. Line circuit for telecommunications system comprising a series impedance (RI; R2) in each of the two line conductors (LT1; LT2) and contacts (Sli, S12; S21, S22) on either side of these two impedances enabling a selective connection from their terminals towards the switchboard (SLIC) or respectively towards the line (LT1; LT2), characterized in that these contacts are made up of two pairs of electronic contacts, where the first (Sli, S12) connects the line to the impedances and the second (S21, S22) connects these to the central unit (SLI C), and that only the first pair of electronic contacts (Sil, S12) is provided with a power supply protection circuit (Ril; R13, R14; Q6) (according to claim 8). 32. Line circuit for telecommunications system according to claim 31, characterized in that the first pair of electronic contacts Sil, S12) is also provided with a secondary protection circuit for power supply (D21, Q5, R12; Q4) (as mentioned in claim 13). 33. Line circuit in a telecommunications system according to claim 31 or 32, characterized in that it also comprises detection equipment (FC) which is connected to the first pair of electronic contacts (Sil, S12) and is able to provide a signal indicating that the voltage above at least one of the electronic contacts exceeds a predetermined value. 34. Line circuit for telecommunications system according to claim 2 or 33, characterized in that the detection equipment (FC) comprises a detection circuit (R15/18, Q7/8, D22/23, Pli, N14/15) with a first input part (R15, Q7) connected to the first biased contact (S) in the first electronic contact (Sil) in the first pair (Sli, S12), a second input part (R16, Q8) connected to a first biased contact to the second, electronic contact (S12) in the first pair and an output part (Q7/8, D22/23, R17) connected to an indication circuit; (Arrow, N14/15, R18) which is also part of the detection equipment and which is able to provide, at an output terminal (FQ ), the indication signal which is a function of the voltage across at least one of the biased contacts (S). 35. Line circuit for telecommunications system according to claim 34, k a. r, a c t e r i s e r t in that the first (R15,_Q7) and second (R16, Q8) input part to the detection circuit (R15/18, Q7/8, D22/23, Pil, N14/15) are each made up of the base and emitter electrodes of an NPN transistor (Q7; Q8) which are respectively connected between the limiting equipment for power and one of the terminals of the biased contact (S), that the output part is made up of the collector electrodes of The NPN transistors, to which a first DC supply terminal (VDD ) is connected via a first resistor (R17) in series with the respective diodes (D22; D23), that the indication circuit (Arrow, N14/15, R18) comprises a PMOS ( Arrow) and a first NMOS (N14) transistor, whose gate electrodes are both connected to the connection point between the first resistance (R17) and the diode (D22, D23) whose drain electrodes are interconnected, and whose source electrodes are respectively connected to the first (VDD ) and other (Vgs ) DC supply terminal, and that they are common drain electrodes of the PMOS and the first NMOS transistors are connected to the gate electrode of a second NMOS transistor (N15), whose source electrode is connected to the second DC supply terminal (Vss ) across a second resistor (R18), and whose drain electrode is connected to the output terminal (Fq)'« 36. Line circuit for a telecommunications system according to any one of claims 31 to 35, characterized in that it comprises third and fourth additional pairs of electronic contacts, the third pair (S31, S32) connecting the impedances (RI; R2) on the line side (LT1) ; LT2) with a first auxiliary circuit (TC) and the fourth set of contacts (S41, S42) on the central side (SLIC) connects them with a second auxiliary circuit (RC).