PH26355A - Semiconductor devices - Google Patents

Description

This invention relates to semiconductor devices ’ and in particular bipolar transistors.

According to the present invention there is pro vided a method of manufacturing a bipolar transister with semi~self-aligned base contacts inoluding the steps of forming a base region of one conductivity type in a surface region of the other conductivity type of a silicon substrate, forming an element on the surface and in contact with the base region, the element being doped to be of the other conductivity type end comprising the exitter of the transistor, forming a pair ef base aone tact regions of the one conductivity type in said sur fagce region in contact with the base region and en opposite sides thereof by implantation and using the element as & mask, and forming a collector contact of the other conductivity type in said surface region and spaced apart from the base contact regions, i Embodiments of the invention will now be dese oribed with reference to the accompanying drawings, in whiohs

Figs 1 illustrates in cross-section a bipelar/ (M03 structure including a bipolar transistor according to one embodiment of the present invention;

Fig. 2 illustrates the bipolar transistor ef

Figo 1 formed in a p-well rather than an n-well as .

Co Can illustrated in Fig. 1, and

Figse 3 to 7 illustrate in cross-section various stages in the manufacture of a bipolar/cMOS structure with n wells, )

The bipolar/CMOS structure illustrated in Fig. 1 comprises a bipolar transistor 1, an n-channel NOS transistor 2 and a p-channel MOS transistor 3¢ The transistor 2 is formed directly in a p-type substrate 4, whereas the transistors 1 and 3 are formed in n-walls 5 and 6, respectively, provided in the substrate 4. The ' , n~channel transistor 2 is formed by conventional CMOS processing and includes nt source and drain regions 7 and 8 respectively, external eleatrical contacts 9 and 10, provided for example by metallisation, to the source and drain regions 7 and 8, a polysilicon gate © 11 together with gate oxide 12, a p' contact 13 to the substrate 4, an external electrical contact 14 te the 5 gontsot 13, provided for example by metallisatieng and isolating oxide 15¢ The gate 11 is also externally ) electrically cennected by means not showne The p-chan~ nel transistor 3 is also formed by conventional CMOS processing in the n~well 6 and inoludes pt source and drain regions 17 and 18, respectively, external electri= oal oontacts 19 and 20, provided for example by metal= > lisation, to the source and drain regions 17 and 18, a / . . | RE “3

. . \ , , - 26355 polysilicon gate 21 together with gate oxide 22, an nt contact 23 to be n~well 6, an external electrical com= taat 24 to the at oontact 23, provided for example by metallisation, and isolating oxide 15.

As will be apprecisted from Fige 1 the bipelar transistor 1 is very similar in cross-section te the p= channel transistor 3 and can in fact be made in inte. grated form with the CMOS devices by the addition of on- ly two extra masks to number employed for the standard

CMOS.. process. The bipolar transistor 1 employs the n= well 5 as its collector and has an n* collector contact 25 thereto and an external electrical contact 26, pre- vided for examples by metallisation. The base of tran- sistor 1 is comprised by two pt contact regions 27 and 27a joined by a p bridging region 28 with two external electrical contacts 26a and 26b as illustrated, and the emitter is comprised by an n' polysilicon region 29, whieh contacts the p region 28, there also being an external ] electrical contact (not shown) to the emitters 0 The bipelar transistor 1 includes elements squie valent to those of p-channel transistor 3 and manufactured concurrently therewith through the same bipolar structure may be manufactured independently thereof. The two extre masks required for the production of the polysilicen 23 efiitter transistor 1 are for defining the implant re-

quired to produce the base region 28 and for opening the "gate" oxide 30 to bring the polysilioon into cone tact with the base region 28 In Figs. 1 and 2 the gate oxide is indicated separately from the remaining isolating oxide 15 although it is formed concurrently with part of the isolating oxide 15 as will be more apparent from the description of Figs. 3 to Be

Thus the bipolar device is fitted directly into n-well CMOS technology, the n-well being used as the . gollector. For use in a p-well technology an additional n implant, for example phosphorus or arsenic, is needed.

This step can be implemented part of the way through the powell drive in. Due to different thicknesses of oxides : in the well and field areas of a non~masked implant can’ : be used for the n-well, although a masked implant can alternatively be used This produces an n—-well 5 within the pewell 5' (stacked wells), which again is used as the collector region of the bipolar device, as illuse trated in Pige 2.

The basic processing stages employed to fabricate : the structure of Fige 1 will now be outlined with res ferences to Figse 3 to 8, Using a first mask and photo- resist (not shown) metype wells 36 and 37 are defined in a p-type substrate 32, for example by ion implantes tion of phosphorus and /subsequent driving-in a convene . ' 5 w tional manner. Using a second mask (not shown) a layer of silicon nitride 31, or silicon nitride on silicon dioxide, deposited on the surface of the p-type silicon substrate 32 is patternsd to distinguish between device areas and areas in which field oxide is to be grown.

Areas of nitride 31 are left on the surface of the substrate 32 at positions corresponding to the deviee areas, as indicated in Fig. 3. Field dopant (not shown) may be implanted into the surface of substrate 32 by use of suitable masking shrough the windows opened in the nitride layers 31, by for example ion implantation of boron and/or phosphorus. The substrate is then oxidised in order to form field oxide 33 in the windows. The areas of nitride 31 are etched away and the substrate further oxidised in order to obtain thin oxide areas 34 between the thick field oxide areas 33 (Figs 4)e A third mask (not shown) is employed to define a window 40 in a photoresist layer 41 (Fig. 5), through which window p~ type dopant, for example boron, is ion implanted to pro- duce a base region 42 for the bipolar transistors This third mask is one of the additional two masks referred $0 abeve., Using a fourth mask (not shown) end an appro- priate photoresist layer a window 43 is opened in the thin oxide area covering base region 42, The alignment 5 48 not oritical as will be apparent frem the following. / .

Lo Ce.

\ 26355

If an interfacial oxide is required for the polysilie oons transistor a suitable treatment can be used now

This fourth mask is the ether additional mask. The photoresist is removed and a layer of undoped polyorye- talline silicon deposited and ion implanted with As er

Pe It is then patterned to produce a polycrystalline emitter 44 and gates 45 and 46 (Figs 6)¢ Then with the polysilicon 44 and 45 together with certain areas of the thin oxide area protected by appropriate patternsd photo- resists 4la, pt dopant for example boron is implanted oo to provide base contact regions 47 for the bipelar dew vice, the substrate contact 48 for the n-channel MOS transistor and the source and drawing regions 49 and 50 for the p-channel MOS transistors Using a further mask a layer of photoresist 51 is appropriately patterned to : define windows whereby an nt dopant, for example arsenic, is ion implanted to provide collector contact 52 for the bipolar device, source and drain regions 53 and 54 for the n-channel MOS transistor and the well contact 55 for the p-channel MOS transister (Fige 7). The photoresist 51 is removed and the water is oxidised and a layer of

PeS.Ge (phosphosilicate glass) deposited to produce an "oxide" layer of the thickness of layer 15 of Figs le : Using another mask windows are opened in the oxide for the provision of the requisite electrical contacts te et Cay “Tw . i the underlying regions, the thus processed substrate is then, for example, metallised and the metal pate terned as appropriate using yet another mask to preducs a structure equivalent to Fige lo Further masking and processing may be employed as is conventional for threes hold tailoring of the n-channel and p-channel MOS tran-~ sistors,

By using the bigh efficiency polysilicon emitter structure the doping levels of the base and collector regions of the bipolar transistor can be optimised te produce low base and collector series resistance whilst still achieving a high current gain. This latitude is not available is conventional bipelar transistors.

Whilst the source and drain regions of the CMOS transistors ape produced in a fully aligned manner by , virtue of the polysilicon gates, the emitter of the bis polar device is only semi~self-aligned with the base comprised by regions 42 and 47, although the performance is not affected therebye

Bipolar transistors with the structure illus- trated in Fig. 1 have been manufactured and found te have very high performance.

Whereas polycrystalline silicon is employed in the specific embodiments described above for the bipolar transistor emitter, this is not the only pessible mates ) Ce.

rial, Other materials may be used provided they have suitable properties, The material may be conductive material incorporating a source of carriers and a do- pant for forming the emitter Examples of materials which may be used instead of polycrystalline silicen . are oxygen doped polysilicon, refractory metals or re= ‘ fractory metals silicides, amorphous silicon (hydree genated or otherwiss).

The doped polperystalline silicon may be manus faotured by a process as described in copending GB "

Application No. 8504725. , ’ . -9w

Claims (1)

CLAIMS:

1. A method of manufacturing a bipolar tran- sistor with semi-self-aligned base contacts including the steps of forming a base region of one conductivity type in a surface region of the other conductivity type of silicon substrate, forming an element en the surface and in contast with the base region, the element being doped to be of the other oonductivity type and comprise ing the emitter of the transistor, forming a pair of . base contact regions of the ene conductivity type in said surface region in contact with the base regien and on opposite sides thereof by implantation and using the elements as a mask, and forming a collecter contaet ef the other conductivity type in said surface region and spaced apart from the base contact regions. 2¢ A method of manufacturing a bipolar trane sigtor as claimed in Claim 1 wherein the surface region is a well of the other conductivity type in a substrate of the one conductivity types 3s A method as claimed in Claim 1 wherein the element is of polycrystalline silicen. : 4s A method as claizmed in Claim 2 wherein the element is of polyorystalline silicone . ‘ . : Lo : PETER DENIS SCOVELL Co ; PETER FRED BLOMLEY ° Inventers