PH26661A - Semi conductor die attach system - Google Patents

Semi conductor die attach system Download PDF

Info

Publication number
PH26661A
PH26661A PH33711A PH33711A PH26661A PH 26661 A PH26661 A PH 26661A PH 33711 A PH33711 A PH 33711A PH 33711 A PH33711 A PH 33711A PH 26661 A PH26661 A PH 26661A
Authority
PH
Philippines
Prior art keywords
die
substrate
bonding
alloys
buffer component
Prior art date
Application number
PH33711A
Inventor
Michael J Pryor
Julius C Fisher
Narendra N Singhdeo
Deepak Mahulikar
Satyam C Cherukuri
Original Assignee
Michael J. Pryor
Julius C. Fisher
Narendra N. Singhdeo
Deepak Mahulikar
Satyam C. Cherukuri
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/826,808 external-priority patent/US4929516A/en
Application filed by Michael J. Pryor, Julius C. Fisher, Narendra N. Singhdeo, Deepak Mahulikar, Satyam C. Cherukuri filed Critical Michael J. Pryor
Publication of PH26661A publication Critical patent/PH26661A/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/682Shapes or dispositions thereof comprising holes having chips therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/381Auxiliary members
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Description

Ta 2606451
SEMICONDUCTOR DIE ATTACH SYSTEM
This application relates to U.S. Pat. Na, 4,704,626, entitled "Graded Sealing Systems for Semiconductor Package" hy Mahulikar et al., filed July 8, 1985, which discloses a semiconductor package having a graded interface zone formed hetween two fused sealing glasses that are ' disposed between a leadframe and a substrate or cover member. The zone accommodates and relaxes thermal stresses formed from significant mismatch hetween the coefficients of thermal expansion of the leadframe and the cover or hase member.
While the invention is suhject to a wide range of applications, it is particularly suited for semiconductor die attachment and will he particularly described in that cannection, More specifically, a metallic buffer component is dispnsed hetween a metallic substrate and a semiconductor die ta dissipate thermal or mechanical stresses caused hy thermal exposure.
Semiconductor dies are typically attached to hermetically sealed packages with a bonding composition of various metals or polymers. These bonding compositions usually melt at a relatively high temperature in order that they can withstand the processing temperatures required to hermetically seal a
BAD ORIGINAL J
1 Le
AE
Tr 60 26 Wi NY A package, i.e, above 400%, Typical bhonding materials and techniques are disclosed in articles entitled "Die
Randing & 30 Packasing Sealing Motervials", hy Singer in
Semiconductor Tnicraational, Dec, L933 and "A New Metal 3 BMysiom Coe hie Avi ochpent" hy Windep ef al, in Proc,
Teoh, Coosa dose, dab, Blectran, Packos, canf, 28ND,
L922, pans TLH-72T alan U,85, Pat, Ho, 3,593,412 discloses o anique atiachment svatenm.
In a typical auaemhbly operation, a semiconductor die oo inledgeated ciccnit is placed in a cavily of a hase + wher containing the bonding composition, The haze iw then heated to melt the bonding composition and 3 cedb epee the die within the cavity of the hase,
Son rae guently, the cavity is covered with a lid and heat - RB} 156 is again applied to seal the lid te the hase and form an mr hermetic enclosure for the die, Lid sealing
Ar temperatures are typically about 400°C, to about 450°C,
Wo
Ba : Examples of this type of process are disclosed in U.S.
Ju! Pat. Nos. 4,229,758 and 4,487,638, "When the hane and lide of the hermetically sealed
Ll semiconductor packages are formed of metal, such as
Ph aril selected copper alloys, the semiconductor die, typically = silicon, is directly attached to the metallic substrate,
Ci Unlike the low degree of mismatch between coefficients pia 25 of thermal expansion (CTE) of the components and the die sel which is common to the conventional ceramic packages,
SRN ih there is a very large mismatch between the coefficients i of thermal expansion of the silicon and the metallic i substrates, i.e. about 100 to about 130x10~7 in/in/°cC.
TEE a0 By contrast, the mismatch in coefficients of thermal
Cl nh
Ly expansion of alumina and silicon is only about 15X1077
SE BAD ORIGINAL 9
Ee 26661 in/in/"c, .
The micmateh of CPF pesuits in Che formnbion of lavge strains and resulting thermal stresses during thermal cyelinge, Por example, when a silicon die is altbached bo a wel ab Cc nhetento will aoconventionall gold- 2% wilicon soaliag wmebal, it iu processed at wn temperate of ahont 40070, After the die in attached } to the substrate, they are cooled down to room temperature, Very often, thermal stress canaed by the
Larize mismatch in their CTH causes Fhe di to either crack or separate at the interface from the suhstrate, oo The problem from a large mismatch in CTE was ) witvated in a neaber of experiments wheo oo a silver a - backed, silicon die was directly attached to a gald yo
TRI 15 rlated, copper alloy substrate having a coefficient of a . thermal expansion of ahout 170X10°7 in/in/°C. The
Bo gh sealing or bonding materials were either conventional i Co gold-2% silicon die attach alloys or a solder comprised i or of ahout 25% silver, 10% antimony and the balance tin. 0 20 Using the gold-2% silicon, attachment of the gilver
Hom ia backed, silicon die to the copper alloy substrate was
Ca unsuccessful because the die typically fractured on ca cooling to room temperature hecause of the large
Dit mismatch in the coefficients of thermal expansion
A 25 between the die and the copper base alloy, i.e. about 3 i 120x107 7 in/in/°c. : By contrast, die attachment with the more did compliant solder was successful. However, the die did
Ho start to fracture after five cycles of thermal shock
IE a0 testing wherein the device was heated from room i temperature to 1509C. in a liquid and subsequently 5
Co 3 BAD ORIGINAL 9 conled to -65°C. in a liquid. The die attach must withstand this type of thermal shock testing for at least 15 cycles to meet MIL-STD-883B, method 1011.3, condition C. =
It is a problem underlying the present invention to provide a semiconductor die attachment ayvatem for attaching a semiconducter die te =a substrate which is able to withstand the stresses resulting {rom thermal cycling of the die and substrate. . 10 Tt is an advantage of the present invention to provide » semiconductor die attach system and process of attaching the system which ahviates one ar more of the limitations and disadvantages of the described prior arrangements, oo 15 It is a further advantage of the present invention : | to provide a semiconductor die attach system and process - . of attaching the system which ig able to dissipsi= i i thermal stresses formed hetween a semiconductor die sol : a substrate, . Co 20 It iz a yet further advantage of the present
Lh invention lo provide a semiconductnr die attach sysiow ai and process of attaching the system wherein a huffer conponent disposed hetween a semiconductor die and a
Lk enbuatrale provides a stress relaxation path to dizssipala
Lp a 25 thermal etrycames, iy
Se 1 iw anciher adyanlege of the presoot invenlkbion : Ln provide a semicondnclor die attach system and process silks of atiaching the avetom wherein the buffer component is
Eid a silver-Lin alloy,
Lo a an 11 de still another sndvantage of the present : invention to pravide a somi etlor die attach system 3 A :
BAD ORIGINAL I t and process of attaching the system wherein the buffer component is a nickel-iron strip bonded with a silver- tin alloy.
Accordingly, thors Voorn Loon provided a semiconductor die attach system and process of attaching ] the system adapted for attaching a semiconductor die to a metal or metal-ceramic substrate. in one embodiment, a metallic buffer component for dissipating thermal stresses is disposed hetween the substrate and the semiconductor die to dissipate styvesses rreated hy thermal cveling of the suhstrate and the die, The metallic component is preferably sealed hetween the } substrate and the die with a silver-tin sealing
CL composition. In another embodiment, a filver-tin . i to
Po 15 sealing composition may be used alone to bond a die to a substrate and dissipate stresses from thermal cycling. ) The invention and further developments ‘of the - invention are now elucidated hy means of the preferzs? embodiments in the drawings. oo 20 IN THE DRAWINGS
Co FIG. 1 illustrates a semiconduclor die attach ‘ i system including a puffer layer in accordance with the present invention,
Fic, vo dillnctuvates a semiconductor die attach
ARS 7h sviaien incorporobing oxidation resistant. layers and a
Ld buf ter Javer,
Sot ah Fic, 3 illustrates a semiconductor die attach
Hh gystem incorporating a puffer layer, harrier layers and
HE oxidation resistant layers. fr
Pl nu F1G. 4 illustrates a sen icondnctor die attach 5
J
BAD ORIGINAL £J system with a silver-tin zolder for attaching a die to a substrate,
FIG. 5 illustrates a semiconductor package,
A semiconductor die attach system 10 for attaching a semiconductor die 12 to a metal orp metal ceramic substrate 14 1g dllhasteatad in Prag, 1. Structure LA ia : disposed between the substrate U4 and Che die 12 {ov diggipating thermal stress caused by thermal cycling. } Seal components 18, 19 attach the thermal stress dissipating strurture to hoth the metallic substrate 14 and the semiconductor die 12.
The present invention is primarily directed to forming a semiconductor package wherein the substrate or
Co hase is formed of a metal having a relatively high coefficient of thermal expansion (CTE) in the area of
Cee ahout 170X107" in/in/®C. The semiconductor die which is to be attached to the substrate typically has a much lower coefficient of thermal expansion of about 50X10” 7 in/in/"cC. The semiconductor die is usually attached to the base by a gold-gsilicon alloy at ahout 400°C, or a solder at about 300°C, However, it has heen found that the semiconductor die may he attached to the substrate with a sealing or bonding material of an alloy formed of - from about 20 to about 40 wt. % silver and about 80 to about 60 wt, % tin. Preferably, the composition of the sealing material would he about 25 to about 35 wt, % silver and about 75 to about 65 wt. %¥ tin. The sealing material would be used at a temperature range of about 350°C, to about 450°C. and preferably at ahout 390°C. to a0 about 410°C,
Another bonding material consists essentially of . 6 BAD ORIGINAL 9
I
TTT TTT Te ee eee eee a ahout 5 to about 20 wt. % copper and i balance essentially indium. Preferably, the composition of this alloy consists essentially of about 5 to about 13 wt. % copper and the balance easentially indium, still another bonding material consists essentially of about 2 to about 20 wt, % Lin and the halance essentially lead,
Preferably, the composition consists essentially of [ ahout 4 to about 8 wt, % tin and the halance essentially : lead.
With a silver-tin sealing materinl and with the other honding materisls, the surface of the die to which : ) it is attached requires an oxidation resistant layer, as
Ci described below, hecause the silver-tin or other bonding : RH : materials do not wet the silicen or other typical
Ea 15 materials of which the die is formed. In either case, :
SE die fracture typically occurs on cooling to room
Cn temperature hecause of the large mismatch in the
TE coefficients of thermal expansion hetween the base and . ho the die, i 20 The present invention overcomes this problem hy
Cl inserting a thin metallic or non-metallic buffer ih component between the substrate and the die. The buffer : » dissipates the thermal stresses caused by the strains fin which are created as the die and substrate are cooled
A 25 down to room temperature. The buffer preferably has a :
CRANES
Ri coefficient of thermal expansion which is much closer to
LE the die than to ths =suhstrate., Then, as the die attach
ChE
Ge system hegins to cool down, the strains caused hy the 1H vy mismatch in coefficients of thermal expansion occur
TE 30 - between the buffer and the substrate instead of between
Ne
Ch the buffer and the die where the coefficients of thermal
Er ’ lao ORIGINAL 9 ie | - nN | 5 oC expansion are more closely matched. The advantage to locating the larger differential in coefficients of thermal expansion hetween the metal buffer and the metal substrate is that the metal to metal band at the hb huffer-suhatrate interface is typically ductile and better able to withatand stresses and deformation, On the other hand, it is important to reduce stresses and deformation at the interface af the buffer and the die a hecause the semiconductor material is very brittle and : 10 not ahle to withstand any significant deformation, In fact, any stresses hetween the brittle semiconductor ! material and the metal huffer is likely to cause oo cracking of the semiconductor material or separation at. :
Ka = the die~substrate interface. a - 15 | Referring to FIG. 1, the component for digsipating thermal stress preferably comprises a thin, buffer eh component 20 of a controlled-expansion alloy having a
Ll thickness of about 1 tn about 20 mils. Preferahly, the a. thickness of the buffer is hetween about 2 to ahout 8 oo 20 mils. It is important that the buffer is relatively
Ear thin hecause it is designed to provide a path of stress
Ne relaxation between the semiconductor device 12 and the - | substrate 14, Since both the semiconductor device and the substrate 14 are relatively thick and rigid, it is gh 25 important that the buffer component 20 be relatively
Sh thin in order that it provide the flexibility and i deformation necessary to carrying out its stress vo ; relaxation function. In fact, the buffer component may gh : deform inte the plastic region to compensate for the 3B NEE 5
TE a0 “strains generated during the cooling period after die
RA 0 | attachment. However, even radical deformation 8
BAD ORIGINAL 9 al
EE ————————epepeet eter re ——————— of this nature does not significantly effect the operation of the semiconductor device as long as the latter neither cracks nor separabtes at its interface with the buffer component.
The huffer companent al=o has a coefficient of thermal expansion of between nhoul asxy0”? tao about 100x10”7 in/in/°¢. Preferably, the hut fer component has i a CTE of about 40x10"7 to about g0x10~7 in/in/%C. In oF general, it igs desirable that the coefficient of thermal : expansion of the huffer component he compatible and relatively close to the CTE of the semiconductor die.
The buffer component may he constructed of a metal or alloy or ceramic having a low CTE selected from the
Co . group consisting of tungsten, rhenium, molybdenum, , alloys thereof, and nickel-iron alleys and ceramics, = Several examples of particular nickel~iron alloys
KE include 42 Ni-58 Fe, 64 Fe-36 Ni and 54 Fe-28Ni-18 Co.
Co It is also within the terms of the present invention to form the buffer component of any metal or alloy which is ahle to meet the requirement for a suitable coefficient _ of thermal expansion as set out hereinabove,
As illustrated in FIG. 3, in order for the : material of the buffer component 20" to farm a strong seal with the seal or bonding components 18", 19", it is
Co 25 nften necessary to form first and second barrier layers . in 42 and 44 on opposing surfaces 28" and 28" of the buffer component. Throughout the specification, primed, double oo Li primed, triple primed and quadruple primed reference
Dod ' : Lo hE numerals indicate components which are substantially the hy 30 . same as the components identified by the same unprimed reference numerals. The harrier layer is typically 9 -
EE BAD ORIGINAL J formed of a materia! :. om the group consisting of nickel, caohalt and alloys thereof. However, it is also within the terms of present invention to form the barrier layer of any suitahle metal or alley which prevents interdiffusion hetween the buffer material and the oxidation resistant layer formed on the barrier layer as described directly below. The barrier layer also enhances the bonding of the oxidation resistant layer, descrihed hereinhelow to the buffer or substrate. . 10 The barrier layer is applied by any conventional means sich as electroplating to thickness of about 1.5 to oo about 10 microns. Preferahly, the thickness of the harrier layer is about 2 to about 3 microns, :
Co ‘ - . Oxidation resistant layers 22" and 24" are formed . . 15 on the barrier layers 42 and 44 respectively. The . oxidation resistant layers are typically formed of a . HE material selected from the group consisting of gold, h silver, palladium, platinum and alloys thereof. These metals are particularly chosen for their ability to 20 resist oxidation at the high sealing temperatures to a which they will he subjected. Typically they are plated oo onto the harrier layer at a thickness of ahout 1,5 to about 10 microns. Preferahly, the thickness nf the oxidation resistant layer is about 2 to about 3 - 25 microns. (It is within the 8s8cope of the present
N invention to plate an oxidation resistant layer directly onto a desired surface without an intermediate barrier layer. ' The substrate 14" may he formed of a metal or 30 alloy but may he formed of any other material such as a ceramic or a cermet having a high coefficient of thermal
J ORIGINAL P ee
, expansion of more than ahout 140X10-7 in/in/oC,
Typically, the substrate material has a coefficient of thermal expansion of ahout 160x10”7 in/in/C. As with the buffer 20", it is deairahle to form a barrier Layer 38 on the surface 31° of the zsuhstrate 147, This harcier layer ia foemel of materials suhatanbially the aame as those mentioned with regard to the harrier layers 42 and 44 on the huffer 20", Further, an oxidation resistant layer 30° may he formed on the barrier layer 238. The layer 230' iz farmed of the same . types of materials as selected for the layers 22" and 24" on the buffer 20". : The seal or honding components 18, 19 is a sealing . material such as an alloy having a melting point of less : tL 15 than about 450°C. Typically, the seal is an alloy
LE selected from the group consisting of gold-silicon,
E ‘ gold-tin, silver-tin and silver-antimony-tin. Most commonly, the seal material is a gold-2% =ilicon which melts at about 363°C. However, it has been found that a silver-tin alley provides an excellent, relatively . ' unexpensive sealing material. The sealing material is preferably formed of from about 20 to about 40 wt. % silver and about 80 to about B60 wt. % tin, Preferably, the composition of the sealing material would be about oo 25 25 to about 25 wt, % silver and about 75 to about 65 wt. . % tin. This material would be used at a temperature range of about 350°C. te about 450°C. and preferably at about 390° to about 410°C. An important quality of the sealing material is its ability to bond tao the substrate, the buffer component had the semiconductor die. In order to enhance this bonding, each of the : 11 " ap ORIGINAL J \
components typically hag an axidation resistant layer as mentioned hereinabove,
The semiconductor die 12 ia typically formed of a material from the group consisting of silican, gallium arsenide, silicon cavhide and combivations thorveafl, In order far the die 12 to he sealed to zeal component 19, an oxidation resiztant Tayer may be disposed on the surface of the die, This layer is selected of any of the materials which are used to form the oxidation resistant laver on the buffer component, Preferahly, this material would be the same as the other oxidation resistant layers used throughout the die attach system.
To further understand the present invention, an ’ | explanation of the process by which the semiconductor © 15 die is attached to the buffer component 16’ and metal oo oo substrate is provided herein with reference to FIG, 3.
The substrate 14" and buffer 20", preferably have a harrier layer and an oxidation resistant layer formed on their surfaces hy any desired process, such as electroplating, The die 12" typically has an oxidation resistant layer 32' on the surface which is to he bhonded. The base 14" is first heated on a stage to a temperature of about 165° to about 400°C, This occurs in an inert or reducing atmosphere to prevent oxidation of the substrate. The redncing atmosphere is commonly nitrogen-4% hydrogen while the inert atmosphere is typically either nitrogen, argon, helium or neon.
However, it is also within the terms of the present invention to form these types of atmospheres with other conventional gasses,
Once the substrate has heen heated tao the desired y 12 DAD ORIGINAL 9 temperature, a strip of the seal component 18", preferably the size of the die 12" is disposed on the surface of the oxidation resistant layer 307, Then the huffer stvuature 16' is stacked opto the material 18",
Then a strip af waterial 13" essentially the same size ar Lhat disposed holtween the substrate and bulfern component is disposed on Lop of the buffer component.
Finally, the semiconductor die is placed on the seal componént 19" so that its oxidation resistant layer 32' : is in cantact with that seal components 19". The entire assembly is heated until the seal component melts and honds the entire structure together. Typically, the semiconductor die is moved or scrubbed on the seal . component 19" to ensure proper wetting of the layer 32’ sa that the die is securely bond to the buffer.
Finally, the sealed assembly is removed from the heat vo and cooled to room temperature, Standard - interconnection techniques may be applied as required to connect the semiconductor die to a lead frame.
Although the invention preferably includes a sealing component 18 hetween the substrate and the buffer 20, it is also within the terms of the present invention to eliminate the sealing component 18 and spot : weld the buffer directly to the substrate 14. This may be accomplished by applying heat and pressure for the — time to achieve a degree of melting sufficient to attain solid state diffusion to bond the buffer directly to the substrate, This may further be accomplished without a barrier layer between these components, An embodiment of this scope would be illustrated in FIG. 1 without the bonding layer 19, te BAD ORIGINAL 9)
Lo-
ee ———— Ee ——————————— J
Referving to the cmbadiment as shown in FTaQ. 1, n basic die attach svstem 10 embodying the concepts of the present invention is set ont, The component. 16 (or dissipating thermal atpess preferably comprises a thin : . 5 buffer 20 of a controlled cxpansion alloy as deseriboed previously in the acpocifical.ion, :
The honding ov s=eald ng components 18, 19 are selected from a bonding material such as an alloy having a melting point of less than ahout 450°C. Although the alloy honding material may he selected from the group : consisting of gold-silicon, gold-tin, silver-tin, silver-antimony-tin and mixtures thereof, it is preferably a silver-tin alloy, The silver-tin alloy honding material preferably congists essentially of © 15 about 20 to about 40 wt. % silver and the balance essentially tin. More preferably, the composition of this honding material alloy consists essentially of about 25 to about 35 wt, % silver and the balance essentially tin. The honding material is applied in a temperature range of ahout 350° to ahout 450°C. and - | preferably in a range of about 390° to ahout 410°¢. An oo important quality of the honding material is its ability to adhere to the substrate, the buffer component and the semiconductor die, In order to enhance this bonding, each of the components may, if desired, have an } oxidation resistant layer or coating as described herein.
The substrate 14 is preferably formed of a metal or alloy but may he formed of any other material such as a ceramic or a cermet having a high cnefficient of thermal expansion of more than ahout 140X107 in/in/%cC. 2)
H BAD ORIGINAL J
L_
Typically, the substrate material has a coefficient of thermal expansion of about 160x107 inZin/ co, The substrate is preferably provided with a cavity 45 lo receive a die 12, However, it is within the terms nf
A the present invention tao delete the cavity and attach the die onto the npper surface 47 of Fhe snbaeleate,
Referring to 1P14a, 2, there iz illustrated a semiconductor die attach system 21 with first and second oxidation resistant layers 22 and 24 provided on the opposite surliaces 26 and 28 of the hnffor component. 20°,
Further, oxidation resistant livers 20 and 32 are : provided on surfaces 24 and 36 of the substrate 14’ and chip 12’, respectively. The oxidation resistant layers : enhance the strength of the bond between the bonding 16 material 18’ and 19' and the huffer component, the substrate and the chip, These layers or coatings are typically formed of a material selected from the group consisting of gald, silver, palladium, platinum and . alloys thereof, It is also within the scope of the present invention to plate an oxidation resistant layer directly onto an intermediate harrier layer provided on the surface of the components as described herein.
To improve the adherence of the die 12° to seal component 19’, 2 fourth axidation resistant layer 32 may . 25 be coated on the surface 36 of the die. This layer is
Cl preferably selected from the materials which are used to form the nxidaticn resistant layers on the buffer : component 20°, Typically, this material would be the same as the other axidation resistant layers used throughout the die attach system.
Referring to FIG. 3, there is illustrated the
Lo e BAD oriGiNAL 8)
Lo.
semiconductor die attach system 40 with first and second harrier layers 42 and 44 on opposing surfaces 26" and 28" of the buffer component 20", The barvier layer has been {ound to be particularvly useful Lo prevent the formation of oxides on the =uvface to which it iw applied, For oxaaple, a happier layer on opposite honding surfaces of a nickel-ivon bualfer componenkb ; prevents the formation of iron oxides on the surface of : the component, These oxides cauld inhihit the honding strength of the bonding material to the buffer component... The bharvier layer may be used in conju’ ion with the oxidation resistant coating because the latter may not prevent oxygen from passing therethrough. For example, if silver alone were used to plate the buffer component. 20", under certain bonding conditions, it would not he a strong hinderance tao the interaction of : oxygen with the buffer component. The result would he the formation of oxides, such as iron oxide which could . leak through the oxidation resistant layers 22",24" and weaken the bond within the honding material 18",19", } The barrier layer 38 may also be coated on the surface 34’ of substrate 14". It is further within the terms of the invention to selectively provide the barrier layer on any surface as desired.
In another embodiment, as illustrated in FIG. 4, } ; the buffer component is deleted and the semiconductor die 12"' is bonded to the substrate 14"’ with only a bonding material 50, It is now thought that the bonding
Co . material alone, if it is compliant enough tao withstand thermal shock testing, can adequately dissipate thermal stress from thermal cycling. However, the buffer 16
BAD ORIGINAL 9 —
component is still advantageous in the system because it distributes stress over the greater thickness of buffer material, as compared to the bonding material ahove.
The prefevved bonding material 50 ig a silver-tin alloy having a composition vhich conuistae cgsent inal Ly of abaud 20 to about 40 wi, % cilver and the bhalanee cumentinlly
Lin, Preferably, the composition of Lhe allay honding material consists essentially of about 25 to ahout 35 wt, % silver and the halance essentially tin. The silver-tin alloy is preferably free of antimony.
However, il may have up to but not including 10% antimony as lang as the silver-tin alloy is compliant enough for the die attachment to withstand thermal shock } testing. i 15 Preferably, the bonding material is processed in a temperature range of about 350°C. to about 450°C. and most preferably in a range of about 390°C. to ahout 410°C. With a silver-tin bonding material, the die attach surface 28" is preferably coated with an oxidation resistant layer 32" hecause the silver-tin does not easily wet the silicon or other materials of which the die is typically formed. An important aspect of this invention is to provide a thick enough layer of the bonding material 50 to dissipate thermal stresses generated by the mismatch in the coefficients of thermal expansion of the die and the substrate. The thickness of the bonding layer is preferably hetween ahout 1 ta about 15 mils.
In order for the honding component to , 30 satisfactorily bond to the substrate 14"’, it may he desirable to coat surface 52 with an oxidation resistant
Hr ‘sap ORIGINAL 9
L layer of material as described above in the apecification, Further, a buffer layer of the material fleseribed in the epbhodiment illustrated in FLG, 3 may he disposed hotween The oxidation Taver and the substrate surface if desired, Pobadimeuts wilhin this scope ave il lvastrated in FLOR. 9 sont 3 alter {the romoval of Che butter 20° or 207, ;
FIG, 5 illustrates a semiconductor package 60 which may incorporate the semiconductor die attach svstems disclosed herein. The semiconductor die package 60 includes a substrate or hase 62, a leadframe 64 and a cover 66, The leadframe 64 is glass sealed hetween the hase 62 and the cover 66, A semiconductor device 12"" is honded to the base 62 hy any of the semiconductor die attach systems disclosed herein, For example, a die attach system, such as a honding material and buffer component hond the die 12"" to the hase 62 as described with regards to the embodiment illustrated in FIG. 1.
Further, oxidation resistant lavers may he disposed on either side of the buffer component as well as on the die 12"" and the hase 62 2s disclosed with regards to the embodiment illustrated in FIG, 2. It is also within the terms of the present invention to incorporate barrier -layers between the huffer component and the oxidation resistant layers as described with respect to . the embodiment illustrated in FIG, 3. Moreover, if desired, the semiconductor die 12"" can be bonded to the hase 62 with any of the bonding materials described herein.
The patents and publications set forth in this application are intended to be incorporated by reference 18 BAD ORIGINAL 9
TT i—————————— - ——— herein,
It is apparent that there has heen provided in accordance with the presenl invention n semiconductor die attach system and process of using {he mystem whieh folly =matiafies the object wy meson aml advantages aot forth heveinabove, While the invealion has boon deseribed in combination with Lhe embodiments thereof, it is evident that many alternatives, modificalionz and variations will he apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended ta embrace all such alternatives, modifications and variations as fall within the spirit and hroad scope of the appended claims, 5) 19 BAD ORIGINAL 9)
L

Claims (4)

Co CLATHS
1. A semicondnetor die ablach syvgtem adapted (or attaching a semiconductor die to a substvrate, comprising: Hh A anbodbyobe having an oc idaiion pemistant laces on Aa rar face adapled to have Lhe somiconduclop: din abtbarhed thereta, aad} nxidation resistant layer being of a material selected from the group consisting of gold, silver, palladium, platinum and alloys thereof, said substrate further having a harrier layer hetween said oxidation resistant layer and said substrate, said harrier layer being of material selected from the group consisting : of nickel, cohalt and alloys thereof; a semiconductor die having an oxidation resistant layer on a surface; means disposed between and handed to said substrate and said semiconductor die for dissipating thermal stress from thermal cycling of said substrate and die, the thermal stress dissipating means comprising: a thin buffer component having a coefficient of thermal expansion of between about 35X10” 7 to about 100X10”7 in/in/°c; bonding means for bonding said buffer component to said substrate and to said surface of said die having said oxidation resistant layer, said bonding means comprising first and second lavers of bonding material disposed against 20 SAD ORIGINAL 9 opposite honding surfaces of said buffer component, aad honding material heing an alloy of silver-tin having from ahout 20% hy weight to ahout 10% by weight bh ci eer Firs aed second oxidation recistant Jayeva aveanged hetweeon said iret and second layers of bonding material and said opposite bonding surfaces of said buffer component. , snlid first and second oxidation reaistant layers heing selected from the group consisting of gold, silver, palladium, platinum and : alloys thereof; and first and second barrier layers arranged hetween said first and second oxidation resistant layers, respectively, and said buffer component, said first and second barrier layers being selected from the group consisting of nickel, cobalt and alloys thereof.
2. The die attach system of claim 1 wherein said buffer component has a thickness of between about 1 to about 20 mils.
3. The die attach system of claim 2 wherein said buffer caompanent has a coefficient of thermal expansion of ahout 4X10” 7 to about gox10”7 in/in/°C.
4, The die attach system of claim 3 wherein said buffer component is constructed of a material selected 3 21 BAD ORIGINA- J from the group consisting of tungsten, rhenium, molybdenum, alloys thereof, nickel-iren alloys and ceramics, 5, The die attach system of claim 4 wherein said subhat rate hoor a coctb ficient of thermal opauaion of more } 7 . . on, . . Chan shoal 40X10 in/in/ Co, caid unbhateate heing na material selocbed from Lhe gronap consisting of metals, alloys, ceramics and cermets. 6, The die attach system of claim | wherein ssid bonding material has a melting temperatore in the range of from ahout 390°C to about 410°C, Inventors: MICHAEL J.
PRYOR JULIUS ¢., FISTER NARENDRA N, SINGHDEO DEEPAK MAHULIKAR SATYAM C.
CHERUKURI » 29 BAD ORIGINAL ben
PH33711A 1986-02-10 1986-04-28 Semi conductor die attach system PH26661A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/826,808 US4929516A (en) 1985-03-14 1986-02-10 Semiconductor die attach system

Publications (1)

Publication Number Publication Date
PH26661A true PH26661A (en) 1992-09-04

Family

ID=25247591

Family Applications (1)

Application Number Title Priority Date Filing Date
PH33711A PH26661A (en) 1986-02-10 1986-04-28 Semi conductor die attach system

Country Status (1)

Country Link
PH (1) PH26661A (en)

Similar Documents

Publication Publication Date Title
US4929516A (en) Semiconductor die attach system
KR950014117B1 (en) Semiconductor die attach system
CA1219104A (en) Copper alloys for suppressing growth of cu-al intermetallic compounds
US5315155A (en) Electronic package with stress relief channel
US4078711A (en) Metallurgical method for die attaching silicon on sapphire devices to obtain heat resistant bond
US4978052A (en) Semiconductor die attach system
US4634638A (en) High melting point copper-gold-tin brazing alloy for chip carriers
US5046656A (en) Vacuum die attach for integrated circuits
EP0090566B1 (en) Semiconductor device package
WO1982002457A1 (en) Die attachment exhibiting enhanced quality and reliability
EP0335744B1 (en) Semiconducting device mounting
JPH0340939B2 (en)
EP0366082B1 (en) Member for carrying semiconductor device
PH26661A (en) Semi conductor die attach system
US5567985A (en) Electronic apparatus with compliant metal chip-substrate bonding layer(s)
JPS6153851B2 (en)
US4357162A (en) Solder composition
JP2001127076A (en) Alloy members for die bonding
JPS6232622B2 (en)
US4816216A (en) Interdiffusion resistant Fe--Ni alloys having improved glass sealing
US4905074A (en) Interdiffusion resistant Fe-Ni alloys having improved glass sealing property
JPS61268032A (en) Semiconductor die bonding apparatus
JPS61181136A (en) Die bonding
EP0039507A1 (en) A process of packaging a semiconductor and a packaging structure for containing semiconductive elements
WO1988005254A1 (en) Process for producing formable and high strength leadframes in semiconductor packages