PL231676B1 - Method for measuring resistance, reactance and impedance module of the two-terminal network powered by sinusoidal alternating voltage and the system for measuring resistance, reactance and impedance module of the two-terminal network powered by sinusoidal alternating voltage - Google Patents

Abstract

The method measures four times the instantaneous value of the voltage across the armature in equal time intervals Ts, which are less than 1/2 of the period T of the voltage, and measures four times the instantaneous value of the current flowing through the armature in the same equal intervals of time Ts. The order of the four measurements of the instantaneous value of the voltage on the branch-connector in relation to the four measurements of the instantaneous value of the current flowing through the branch-connector is arbitrary, provided that the first measurement of the instantaneous value of the voltage on the branch-connector and the first measurement of the instantaneous value of the current flowing through the branch-connector are carried out in the time interval Tp equal to 1/2 of the time interval Ts of the measurements of instantaneous current and voltage values, i.e. Tp=1/2Ts. On the basis of the results obtained from the measurements, the auxiliary parameter θ is calculated, and then the resistance, reactance and impedance modulus of the two-connector supplied with sinusoidal alternating current are calculated. The system includes an analog multiplexer that alternately switches the voltage signals proportional to the 2-wire current and 2-wire voltage to the input of the analog-to-digital converter, and the system performs alternately one measurement of the instantaneous value of the voltage current. The measurement result from the analog-to-digital converter is sent to a queue of eight series-connected buffers of memory units, storing the results of the last eight measurements, which are connected to the parameter calculation circuit, which calculates the value of the auxiliary parameter θ, and then calculates the values of resistance, reactance and impedance modulus measuring the first four instantaneous values of current and four instantaneous values of voltage, and after measuring each subsequent instantaneous value of current or voltage.

Description

The subject of the invention is a system for measuring the resistance, reactance and impedance modulus of a bi-terminal fed with a sinusoidal alternating current, applicable in testing the physical properties of electrical circuit elements and the electrical properties of sinusoidal alternating current circuits; also used in sensor and biosensor systems and networks (medicine) and energy systems.

There are known systems for determining the parameters of the terminal impedance, based on the measurement of the voltage across the terminal block and the current flowing through the terminal block, and then calculating the impedance according to formulas based on the ratio of voltage and current. The most commonly used systems are batch sampling, where samples are collected at regular intervals.

These systems include solutions based on the Fourier transform - FFT, which include, inter alia, the solutions included in patents CN102193031 or WO2011111867, WO03 / 069304, where additionally complex numbers are used. These solutions are characterized by the necessity to collect many samples, usually from at least one period, and relatively high computational complexity, which is their disadvantage, especially in the case of portable battery-powered multimeters. In such multimeters, it is very important to use as little computing power as possible to reduce the microprocessor operating frequency, and thus the electricity consumed, which has a significant impact on the cost of operation and battery life. Collecting samples from the entire period also affects the time of obtaining the analysis results. Additionally, there is often the problem of sampling synchronization with the tested signal, the lack of which causes a leakage of the spectrum and an additional measurement error.

There are also known solutions based on uniform synchronous sampling, not based on FFT, which include, among others, the solution included in the Polish patent application PL399821. It is characterized by the simplicity of calculations and no need to collect samples from the entire signal period. The disadvantage of solutions with synchronous sampling is the necessity to use synchronization systems, most often based on PLL circuits, which causes the expansion and increase in costs of the hardware part of the device.

The essence of the system for measuring the resistance, reactance and impedance module of a bi-terminal supplied with a sinusoidal alternating current, according to the invention, is that the system includes a pair of input terminals to which a source of a sinusoidal alternating voltage is connected, in particular a sinusoidal alternating voltage generator, and a pair of output terminals, connected to the terminal whose impedance is measured. Connected between the pairs of terminals is a circuit converting the two-terminal current into a voltage signal with a voltage proportional to the two-terminal current, in particular a standard resistor connected between one of the input terminals and one of the output terminals together with a differential amplifier measuring the voltage across the standard resistor. On the other hand, to a pair of output terminals, a circuit converting the voltage across the two-terminal to a voltage signal proportional to the voltage across the two terminal, in particular a differential amplifier, is connected. Both output voltage signals from the processing circuits are fed to the inputs of the multiplexer, which switches these signals to the analog input of the analog-to-digital converter, while the output of the analog-to-digital converter is connected to the memory unit buffer containing the value of the last measurement and constituting one of the eight buffers connected in series with each other and containing the values of the last eight measurements. The buffer outputs are connected to the input of the parameter calculation system.

Switching the multiplexer, triggering the measurement in an analog-to-digital converter and triggering calculations in the parameter calculation system is performed by the measuring path controller. The measurement path controller causes four times the measurement of the instantaneous value of current and voltage at the two junction at equal intervals of time Ts, which are less than% of the voltage period T, obtaining the results ui = u (ti), U2 = u (t2), U3 = u (t3) ), U4 = ufa) where ti, t2, t3, t4 are successive times of current measurements, and ii = i (ts), h = i (ie), i3 = ifa), i4 = i (te) where ts, te , t7, te are consecutive times of current measurements, the sequence of making four measurements of the instantaneous value ui, u2, u3, u4 on the two-terminal in relation to four measurements of the instantaneous value of the current ii, ',' 2,13,14 flowing through the two-terminal is optional under the condition that the first instantaneous value measurement of the voltage across the two terminal ui = u (ti) and the first instantaneous measurement of the current through the two terminal ii = i (ts) are made at a time interval T _p that is less than% of the voltage period Ts. If the first voltage measurement is performed, the subsequent buffers contain the values xi = ui, Χ2 = ii, Χ3 = u2, Χ4 = '2, Χ5 = u3, xe = i3, Χ7 = u4, xe = i4, and if the first one is performed

PL 231 676 Β1 current, then the following buffers contain the values xi = ii, Χ2 = ui, Χ3 = h, Χ4 = 1/2, xs = 13, xe = U3, xi = 14, xs = U4. The track controller activates the parameter calculation system after measuring the first four instantaneous values of current and four instantaneous values of voltage, and after measuring each successive instantaneous value of current or voltage.

The described functionality of the measurement path controller is preferably implemented by means of a circuit which comprises a digital clock signal generator, the output of which is connected to the measurement excitation input of an analog-to-digital converter. The controller circuit also includes reset buffer circuits with a length of 8 and a frequency divider with a value equal to 2, reset at the moment of starting the measurements, the inputs of which are connected to the digital signal output from eight memory unit buffers connected in series connected to the analog-to-digital converter informing that in the queue the buffer values have been saved. The output of the reset buffer is connected to the parameter calculator to the digital signal input to trigger the parameter calculation. The reset buffer, when the first seven initiation signals arrive, does not transmit the wake-up signal to the output, while when the eighth and subsequent initiation signals arrive, the buffer transfers the wake-up signal to the parameter calculator. On the other hand, the output of the frequency divider is connected to the digital signal input of the parameter calculation system, which informs whether the current or voltage values are stored in the buffers of the memory units that store the values of the fifth and seventh measurements. If the analog-to-digital converter sends a digital signal to terminate the processing but does not send a digital signal about the end of sampling, or this signal is not sent to the measuring line controller, the signal from the frequency divider is also sent to the multiplexer control input, which is connected to the divider output. However, if the analog-to-digital converter sends digital sampling and processing end signals and they are sent to the measurement circuit controller, the multiplexer control input is connected directly to the output of the second frequency divider by a value equal to 2 contained in the measurement circuit controller, which is reset at the moment of starting the measurements and whose input is connected to the digital signal output of the analog-to-digital converter informing that the converter has finished sampling.

The parameter calculation system is activated after collecting the measurements, i.e. after measuring the first four instantaneous values of current and four instantaneous values of voltage, and after measuring each successive instantaneous value of current or voltage, and calculates the following parameters:

• auxiliary parameter Θ1 according to the formula:

for x ₃ = 0

for x ₃ Φ 0 λ x ² + 4x ₃ (x ₃ + x ₇ ) <0

- + 4x ₃ (x ₃ + x ₇ )

• auxiliary parameter Θ2 according to the formula:

PL 231 676 Β1 • auxiliary parameter Θ according to the function formula:

= / (0, ¾) with the property 'θ _} <<? ₂ ) <ą for o, <e ₂ \ θ _} > / (θ "θ ₂ )> θ ₂ ύ \ 8θ _} > θ ₂ in particular according to the mean formula 1, preferably according to the arithmetic mean formula: g ₌ θ ₁ + θ ^ where if the arithmetic logical unit in the parameter calculation system calculates the value of the parameter Θ satisfying the condition | θ | > 1 - ε, where ε e (0; 10 ^-1 ], where preferably ε e [1 (λ ⁵ , 10 ² ], then this value is changed to the value determined according to the formula:

J (9 = -l + s dfa (9 <0 θ = 1-ε forć?> 0 • auxiliary parameter a according to the formula:

a = 2χ ₅ χ _Ί θ - (x ² + x ² ) • auxiliary parameter b according to the formula:

b = 2χ ₆ χ _ί Θ - (x ₅ x ₆ + x ₇ x _g ) • auxiliary parameter c according to the formula:

c = 2x _ń x _s 0- (x ² + x ² ) • auxiliary parameter d according to the formula:

d = x _s x _& - x ₆ x ₇ • resistance R of the two-terminal:

o when the voltage is measured first, according to the formula:

_n b + d [Ϊ + 0 R = CC-Jc N 2 o when current measurement is performed first, according to the formula:

b + d jl + 0 R-a-I N 2 • resistance X-junction:

o when the voltage is measured first, according to the formula:

o when the current measurement is performed first, according to the formula:

_v db 1-0 X ~ a-JPL 231 676 Β1 • impedance module (hindrance) | Z | dwójnik:

o when the voltage is measured first, according to the formula:

| from | = «

o when the current measurement is performed first, according to the formula:

The coefficient a, present in the formulas for resistance, reactance and impedance modulus, is a characteristic constant for a given measuring system, determined according to the formula:

wherein ai is the ratio ratio between the two-terminal current value and the output value of the first analog-to-digital converter, and az is the ratio ratio between the two-terminal voltage value and the output value of the second analog-to-digital converter. The unit of the coefficient a? is the ampere [A] and the unit of az is the volt [V]. These factors are used to convert the output of an analog-to-digital converter from an integer to a physical quantity of two-terminal current or voltage. The calculated values of resistance, reactance and impedance module are sent by the parameter calculation system directly or indirectly to the interface of the measuring system.

The advantage of the system for measuring the resistance, reactance and impedance module of the bi-junction supplied with sinusoidal alternating current, according to the invention, is the minimum number of measurement samples, the possibility of shortening the measurement time to less than one period of the bi-junction supply voltage, reducing the computational complexity and thus the energy cost and time of determining parameters and simplification method of measurement by eliminating the need to synchronize sampling with a period of current or voltage. Additionally, when determining the values of resistance, reactance and impedance modulus, trigonometric functions involving high computational complexity are not used. Additionally, computational operations are limited to the simplest arithmetic operations: addition, subtraction, multiplication; division and square root. Another advantage of the system is the use of specific formulas for the first measurement of current and voltage, which allows to calculate the next result after each current and voltage measurement, and thus shorten the period between successive measurement results. A special advantage of the system, which distinguishes it from other solutions, is that, assuming no measurement and numerical error, the determined parameters do not have an error resulting from the measurement method, i.e. the obtained result is accurate.

The invention will be illustrated in the embodiment shown in the drawing, in which Fig. 1 shows a general measurement system, Fig. 2 shows a diagram of the UOP parameter calculation system, and Fig. 3 shows a diagram of a measuring circuit controller KTP. In the diagram of the measurement circuit from Fig. 1, the generator G, connected to the input terminals of the measurement line, symbolically represents the system generating the sinusoidal alternating voltage, while the two-terminal D, connected to the output terminals of the measurement line, symbolically represents the two-terminal whose impedance parameters are tested.

The measuring system is adapted to be operated by the user via the INT interface. Through the INT interface, the user can set the operating parameters of the measuring system, start a measurement or read the measurement results. The INT interface is connected by a bi-directional digital bus with the KI interface controller.

The KI interface controller is adapted to work in two modes: in the measurement parameter setting mode and in the measurement mode. In the measurement parameter setting mode, the KI controller supports the INT interface - it downloads the sampling period setting parameter and gets the command to start the measurement. In addition, the KI controller writes the system operation parameter - the clock timing period Tclk using the digital bus in the TC memory unit where the Tclk period is equal to the ADC sampling period T _p = ¹ AT _S , where T _s is the period between successive

With current or voltage samples. The period Tsm must meet the condition Ts, < ¹ ATs, where T is the period of the tested voltage, hence the condition Tclk = T _p =% T must be met.

At the moment of the initiation and measurement command from the INT interface, the KI interface controller sends to the INT interface the information about the start of the measurement and sends a digital signal to the KTP measurement path controller in order to start the measurements. Then, the KI controller suspends its operation in the communication mode, entering the standby mode until the appearance of a digital signal informing the determination of the impedance parameter values from the UOP parameter calculator.

At the moment of the appearance of the signal to determine the parameter values from the UOP system, the KI interface controller reads, using digital buses, the determined parameters of the impedance of the bi-junction supplied with sinusoidal voltage: resistance R stored in the memory unit R, reactance X stored in the memory unit X and impedance module | Z] stored in the MZ memory unit and sends them to the INT interface. Then, the interface controller checks via the digital bus if there is no message on the interface on the completion of the measurements. If there is no message about the end of the measurements, the KI interface controller remains in the measurement mode, waiting for the next signal from the UOP system informing about the next determination of the value of the two-terminal impedance parameters and repeats the entire measurement mode procedure. If the interface controller reads the measurement completion message from the INT interface, the KI controller sends a digital signal to the KTP controller about the completion of the measurements and then returns to the measurement parameter setting mode.

The KTP measuring track controller is responsible for controlling the measuring track and the system for calculating UOP parameters.

The measurement path includes: RW reference resistor, W1 and W2 differential amplifiers, MUX multiplexer, ADC analog-digital converter and eight memory unit buffers: X1, X2, X3, X4, X5, X6, X7, X8. The generator G, connected to the input terminals of the test line, symbolically represents a system generating variable voltage, while the two-terminal D, connected to the output terminals of the test line, symbolically represents the two-point, the impedance parameters of which are tested.

The series-connected two-terminal D and the standard resistor RW are connected to the generator terminals G. The terminals of the standard resistor RW are connected to the inputs of the first differential amplifier W1, which amplifies the voltage drop on the standard resistor RW caused by the flow of current. The inputs of the second differential amplifier W2 are connected to the terminals of the tested two-terminal D. The outputs of both amplifiers W1 and W2 are connected to the corresponding inputs of the MUX multiplexer. The MUX multiplexer is controlled by the KTP measurement path controller. The output of the MUX multiplexer is connected to the input of the ADC analog-to-digital converter, whose external measurement excitation input is controlled by a digital signal from the KTP measuring line controller. The task of the W1 and W2 amplifiers is to condition the voltage across the reference resistor RW and the voltage across the dipole D, respectively, to the ADC range. This means that the voltage at the output of the amplifiers in relation to the ground is directly proportional to the current of the two-terminal point D and the voltage of the two terminal point D, and the gain of the amplifiers is selected so that at a given measuring range the voltage at their output does not exceed the operating range of the ADC. Additionally, the operating range of the MUX multiplexer cannot be smaller than the operating range of the ADC converter. The ADC converter sends two digital signals: one about the end of sampling to the KTP controller and the other about the end of processing (of the entire measurement) to the X1 memory unit buffer.

Additionally, the ADC transmits the measurement result to the buffer of the X8 memory unit via the digital bus. The memory unit buffers X1-X8 have one digital input which initiates writing of the value to the input of the buffer connected to the digital bus. After writing the value to the buffer, its value is fed to the output connected to the digital bus and the digital initiation signal is sent to another digital circuit. These buffers are connected in such a way that the value from the ADC is fed first to the memory unit X8 buffer, then from the buffer X8 to X7, X7 to X6, X6 to X5 ..., X2 to X1, and the digital initialization signal after completion measurement by the ADC converter is fed to the X1 buffer, then from the X1 to X2 buffer, X2 to X3, X3 to X4, ..., X7 to X8. Finally, the digital excitation signal from the X8 memory unit buffer is fed to the KTP measurement line controller. Such a connection scheme means that at the outputs of the X1-X8 buffers there are successively the values of the last eight measurements, with the value of the last measurement in the X8 buffer. The values at the outputs of all X1-X8 buffers are given via digital buses to the UOP parameter calculation system.

PL 231 676 Β1

A detailed diagram of the structure of the KTP measurement circuit controller with digital signals, an external bus, and a TC memory unit is shown in Fig. 3. The KTP controller consists of four elements: a CLK digital clock signal generator, a 8 UBR8 reset buffer system, and two frequency dividers by a value equal to 2 - DF2A and DF2B. The digital signal to start the measurements from the KI controller is the reset signal for all four elements. At the moment of starting the measurements, the reset signal is turned off, which causes the simultaneous start of operation of all four elements. The CLK clock reads the value of the clock period Tclk from the memory unit TC via the digital bus and sets its operating period based on this. The task of the clock is to trigger the measurement in the ADC converter, whose input of external excitation of the measurement is connected with the clock output. When the ADC finishes sampling the voltage on its analog input, it sends an excitation signal to the frequency divider by 2 DF2B, the output of which is connected to the control input of the MUX multiplexer. This solution ensures that after collecting one sample, the multiplexer switches to the second input from the next one sample is collected, ie one sample of the current at the two terminal D and one sample of the voltage at the terminal D. After the end of the measurement, the ADC converter sends the initial digital signal to the cascade of memory unit buffers Χ1-Χ8. After writing the result from the converter to the X8 buffer, the X8 buffer sends a digital initiation signal to two circuits: the length reset buffer circuit 8 UBR8 and to the frequency divider circuit by 2 DF2A. The purpose of the length reset buffer circuit 8 is to count the digital initiation signals on its input. When the first seven initiation signals arrive, the buffer does not transmit the excitation signal to the output, while when the eighth and subsequent initiation signals arrive, the UBR8 buffer transmits the initiation signal to its output, which is connected to the digital input of the external excitation of the UOP parameter calculator (INIT signal) . This means that the initiation signal will be applied to the UOP after the first eight samples are collected and each additional sample is collected by the ADC. The frequency divider by 2 DF2A changes the value of the digital signal to the opposite value at its output each time it receives an initiation signal at its input. The DF2A output is connected to the digital input of the UOP parameter calculator (U / f signal) and informs whether the data of current or voltage samples are stored in buffers Χ1, X3, X5, X7.

The UOP parameter calculation system is used to calculate the measurement data values on the basis of the measurement data sample values collected in buffers Χ1-Χ8. A detailed structure diagram of the UOP parameter computing system along with digital signals and external buses, and buffers of measurement data memory units Χ1-Χ8 and memory units P, O and MS is shown in Fig. 2.

The parameter calculator 0UO (-) 1 waits for the digital excitation signal from the KTP (DF4) system. At the moment of receiving the initial signal, it reads, via digital buses, the values of samples xi from the X1 buffer, xa from the X3 buffer and xs from the X5 buffer and χχ from the X7 buffer and on their basis calculates the value of the auxiliary parameter θι according to the formula:

χ _Ί

2x, * 1 x, - ^ x ² + 4x ₃ (x ₃ + x ₇ )

4x ₃

X, + ^ x ² + 4x ₃ (x ₃ + x ₇ ) 4x ₃ for x ₃ = 0 for x ₃ Φ 0 λ x ² + 4x ₃ (x ₃ + x ₇ ) <0 for x ₃ 0 λx ² + 4x ₃ (x ₃ + x ₇ )> 0 λ x, + 2x ₅ <0 for x ₃ Φ 0 λ x ² + 4x ₃ (x ₃ + x ₇ )> 0 λ Xj + 2x ₅ > 0

Then the UO © 1 circuit uses the digital bus to write the value of the parameter θι in the memory unit Θ1, sends an initial digital signal to the AND gate circuit A1, and goes into the waiting mode for the wake-up signal from the UBR4 chip.

The calculation system for the parameter Θ2 UO © 2 waits for the digital excitation signal from the KTP system (DF4). As soon as it receives the initiation signal, it reads the values via digital buses

PL 231 676 Β1 samples χς from the X2 buffer, x ₄ from the X4 buffer, xe from the X6 buffer and xg from the X8 buffer and on their basis calculates the value of the auxiliary parameter Θς according to the formula:

02 * 8 2x ₂ for x ₄ 02 for x. 4x ₄ 02 ix ₂ ² + 4x ₄ (x ₄ + x ₈ ) for x ₄ 4x ₄ 02 ^X 2 + \ / x ² + 4x ₄ (x ₄ + x ₈ ) for x. .. 4x ₄

= 0 + 0 λ x ₂ + 4x ₄ (x ₄ + x ₈₎ <0 * 0λχ ₂ + 4x ₄ (x ₄ + χ _8)> 0λχ ₂ + 2x _Æ <0 ψ 0 λ x ₂ + 4x ₄ (x ₄ + x ₈ )> 0 λ x ₂ + 2x ₆ > 0

Then, the circuit ΙΙΟΘ2, using the digital bus, writes the value of the parameter Θς to the memory unit Θ2, sends an initial digital signal to the AND gate circuit A1 and goes into the waiting mode for the excitation signal from the KTP test track controller.

AND gate A1 waits for initial digital signals from UO © 1 and UO © 2. After receiving both initiation signals, the AND gate circuit A1 sends an initiation digital signal to the end parameter calculator UOK and goes into the waiting mode for excitation signals from UO © 1 and UO © 2.

The calculator of the parameter Θ UO © waits for the initial digital signal from the AND gate A1. After receiving the initiation signal, the UO © circuit uses digital buses to read respectively the auxiliary parameters θι from the memory unit © 1 and Θς from the memory unit © 2 and calculates the auxiliary parameter Θaccording to the formula:

₌ ^ 1 + # 2 2 where if the calculated value of the parameter Θ meets the condition | <9 | > 0.9999, then this value is changed into the value determined according to the formula:

β = -0.9999 for * <0 <9 = 0.9999 for <9> 0

Then, the UO © system, via the digital bus, stores the value of the parameter Θ in the memory unit ©, sends initial digital signals to the UOK end parameter calculator and goes into the waiting mode for the wake-up signal from the AND A1 gate system.

The UOK end parameter calculation system waits for the excitation signal from the 6 * UO © parameter calculation system. At the moment of receiving the excitation signal, the system reads, using digital buses, the value of the parameter Θ from the memory unit © and the values of samples xg from the X3 buffer, x ₄ from the X4, X5 buffer from the X5 buffer and xe from the X6 buffer and on their basis it calculates:

• parameter value a according to the formula:

a = 2x ₅ x ₇ (9 - (x ₅ ² + x ₇ j which is written by the digital bus in the memory unit A, • parameter value b according to the formula:

ó = 2x ₆ x ₇ 0- (x ₅ x ₆ + x ₇ x ₈ ) which is saved by the digital bus in the memory unit B, • parameter value c according to the formula:

c = 2x ₆ x ₈ 0- (x ² + x ₈ )

PL 231 676 Β1 which is saved by the digital bus in the memory unit C, • parameter value d according to the formula:

which it saves via the digital bus in the memory unit D.

Then, additionally using the value of parameter a stored in memory unit A, parameter value b in memory unit B, parameter value c in memory unit C, parameter value d in memory unit D, which are read using digital buses, the UOK chip reads the digital signal value coming from the KTP measurement path controller (DF8 - U / l signal) informing whether in samples Χ3 and X4 there are instantaneous values of current or voltage, and on the basis of its value, if in the memory unit buffers X3 and X4 there are values of voltage samples at the D terminal, then the UOK system calculates:

• value of the resistance R of the terminal D according to the formula:

which it saves using a digital bus in the memory unit R, • reactance value of the connector D according to the formula:

which it saves via the digital bus in the memory unit X, • value of the impedance module | Z | dwójnik D according to the formula:

i ^z i = ^a JI which it stores over the digital bus in the memory unit MZ.

However, if the memory units X3 and X4 contain the values of the samples of the bi-terminal D current, the UOK system calculates:

• value of the resistance R of the terminal D according to the formula:

b + d ll + 0 R = a-I V 2 which is saved by the digital bus in the memory unit R, • reactance value of the X-coupler D according to the formula:

X-a d-b

Which saves via the digital bus in the memory unit X, • the value of the impedance module | Z | dwójnik D according to the formula:

which it saves via the digital bus in the MZ memory unit.

The coefficient a used in the formulas for resistance, reactance and impedance modulus is a characteristic constant for a given measuring system, determined according to the formula:

^a 2 a- - cr,

PL 231 676 Β1 where n is the ratio between the voltage at the terminal D and the value at the output of the ADC, and 2 2 is the ratio between the voltage at the terminal D and the value at the output of the ADC. The unit of the coefficient on is the ampere [A] and the unit of the coefficient 2 is the volt [V]. These coefficients are used to convert the ADC output from an integer to a physical value for the two-terminal current or the voltage at the two terminal. For the system from Fig. 1, the coefficients are determined according to the formulas:

- ^LSB in,

LSB a ₂ = w ₂ where wi is the gain of the amplifier W1, W2 is the gain of the amplifier W2, R _w is the resistance of the reference resistor RW expressed in ohms [Ω], and LSB is the voltage value corresponding to 1 bit of the ADC expressed in volts [V].

After saving the calculated values, the UOK system sends a digital signal to the KI interface controller informing about the determination of impedance parameters.

If the ADC converter does not send sampling and processing termination signals, but only sends the signal to complete the entire measurement, then the KTP measurement path controller circuit from Fig. 3 is replaced by the circuit from Fig. 4, in which there is no frequency divider DF8, and the digital signal controlling the MUX multiplexer is the output of the frequency divider DF2A.

The KTP track controller system from Fig. 4 can also be used in the case when the ADC sends both sampling and processing termination signals, and the sampling termination signal is not connected to the KTP measurement line controller.

The measurement arrangement of the invention outlined above is to be considered as an exemplary arrangement. The individual elements of the circuit may be in the form of digital or analog circuits. It will be obvious to a skilled person how to implement the individual blocks in order to fulfill their functionality. In one of the possible implementations, the measurement system may be implemented in the form of a processor controlled by appropriate software. In another embodiment, the measurement circuitry may be implemented as an FPGA programmable logic circuit.

Patent claims

Claims (10)

1.A system for measuring the resistance, reactance and impedance module of a bi-terminal fed with sinusoidal alternating current, including: • a pair of input terminals, to which a source of sinusoidal alternating voltage (G) is connected, • a pair of output terminals, to which a two-terminal socket (D) is connected, the impedance parameters of which are measured, • a system converting the two-terminal current into a voltage signal, connected between the pairs of terminals, o voltage proportional to the two-terminal current, • a system connected to a pair of output terminals converting the voltage at the two-terminal to a voltage signal proportional to the voltage at the two-terminal connector, • where both signals with a voltage proportional to the two-terminal current and the voltage signal with a voltage proportional to the voltage at the connected to the multiplexer inputs (MUX) switching these signals to the analog input of the analog-to-digital converter (ADC), • the multiplexer (MUX) is switched by the measuring line controller (KTP), which also triggers the measurement by the analog-to-digital converter (ADC characterized by the that: • the output of the analog-to-digital converter (ADC) is connected to the memory unit buffer (X8) containing the value of the last measurement and being one of the eight buffers (Χ1-Χ8) connected in series and containing the values of the last eight measurements, PL 231 676 Β1, the test track controller (KPT) measures the instantaneous value of the current and voltage at the double junction (D) four times at equal intervals T _s , which are less than% of the voltage period 7, obtaining the results ui = u (ti), respectively, U2 = Ufa), U3 = Ufa), m = Ufa) where ti, t2, t3, t4 are consecutive times of current measurements, and ii = ifa), / ₂ = trust), 13 = ifa), 14 = ifa) where ts, te, i.e., ts are successive times of current measurements, the sequence of making four measurements of the instantaneous value ui, U2, U3, U4 on the dipole D with respect to the four measurements of the instantaneous value of the current ii, i ₂ , ₁₃ , 14 flowing through the dipole ( D) is arbitrary, with the condition that the first measurement of the instantaneous value of the voltage at the junction ui = ufa) and the first measurement of the instantaneous value of the current flowing through the junction ii = ifa) are performed with the time interval T _p equal to% of the period T _s , where the first voltage measurement is performed, then the following buffers (Χ1-Χ8) contain the value i xi = ui, Χ2 = ii, Χ3 = U2, Χ4 = 12, xs = U3, xe = h, xi - U4, xs = 14, and if the first current measurement is performed, then the subsequent buffers (Χ1-Χ8) contain values xi = ii, Χ2 = ui, Χ3 = 12, Χ4 = U2, Χ5 = 13, X6 = U3, Χ7 = 14, xs = U4, while the outputs of the buffers (Χ1-Χ8) are connected to the input of the parameter calculation system (UOP ). the parameter calculation system (UOP) is activated after collecting the measurements and calculates the following parameters: o auxiliary parameter 0i according to the formula: for x ₃ = 0 for x ₃ Ψ 0 λ x _t ² + 4x ₃ (x ₃ + x ₇ ) <0 2x, * i 4x ₃ Xi- ^ x, ^z + 4x ₃ (x ₃ + x ₇ ) 4x ₃ x _t + ^ x, ² + 4x ₃ (x ₃ + x ₇ ) for x ₃ * 0 ax, ² + 4x ₃ (x ₃ + x ₇ )> 0 λ x, + 2x ₅ <0 for x ₃ T- 0 λ X] ² + 4x ₃ (x ₃ + x ₇ )> 0 λ x, + 2x ₅ > 0 -γλ ₃ auxiliary parameter 02 according to the formula: for x ₄ = 0 for x ₄ T Ολχ ^ + 4x ₄ (x ₄ + x ₈ ) <0 2x ₂ ^X 2 4x ₄ ^X 2 ~ yl ^X 2 ^{+ Ąx} A ^X 4+ ^X s) 4x ₄ x ₂ + ^ x ₂ + 4x ₄ (x ₄ + x ₈ ) 4x ₄ for x ₄ # 0 λ x ₂ + 4x ₄ (x ₄ + x ₈ )> 0λx ₂ + 2x ₆ <0 for x ₄ Φ 0λ x ₂ + 4x ₄ (x ₄ + x ₈ )> 0 λ x ₂ + 2x ₆ > 0 auxiliary parameter 0 according to the function formula: about ownership: A </ (0, 0,) <0, 0,> f (0, 0,) i0, for θ _ι <θ ₂ for> θ ₂ PL 231 676 Β1 by the auxiliary parameter a according to the function formula: a = 2χ ₅ χ _ί Θ - (x ₅ ² + Xy) by an auxiliary parameter b according to the formula: = 2x ₆ x ₇ æ? - (x ₅ x ₆ + x ₇ x ₈ ) with the auxiliary parameter c according to the formula: c = 2x ₆ x _g 0- (xg + x ₈ ) o auxiliary parameter d according to the formula: d = x ₅ x ₈ - x ₆ x ₇ o the resistance R of the two-terminal, the value of which is transferred directly or indirectly to the system interface (INT): when voltage is measured first, according to the formula: b + d / l + $ when the current measurement is performed first, according to the formula: b + d / 1 + 0 R = a-I N 2 o the X-double reactance, the value of which is transmitted directly or indirectly to the system interface (INT): when voltage is measured first, according to the formula: b-d Χc V 2 when the current measurement is performed first, according to the formula: _v db 1-0 X ^{= a} - \ a \ 2 o impedance module (hindrance) | Z | doublet, the value of which passes indirectly or directly to the system interface (INT): when voltage is measured first, according to the formula: when the current is measured first, according to the formula: where the coefficient a in the formulas for resistance and the impedance modulus is a constant coefficient determined according to the formula: a, a-a. PL 231 676 Β1 where αι is the ratio between the two-terminal current (D) and the converter output (ADC) value, and a ₂ is the ratio between the two-terminal voltage (D) and the converter output (ADC). 2. The measuring system according to claim The method of claim 1, characterized in that the source of the sinusoidal voltage is a sinusoidal voltage generator (G). 3. The measuring system according to claim The circuit according to claim 1, characterized in that the circuit converting the two-terminal current into a voltage signal is a standard resistor (RW) connected between one of the input terminals and one of the output terminals together with a differential amplifier (W1) measuring the voltage across the standard resistor (RW). 4. The measuring system according to claim The circuit according to claim 1, characterized in that the circuit converting the voltage across the two terminal into a voltage signal proportional to the voltage across the terminal is a differential amplifier (W2). 5. The measurement system according to claim 1, The method according to claim 1, characterized in that if the arithmetic logic unit in the parameter calculator Θ (UO ©) calculates the value of the parameter Θ satisfying the condition > 1 - ε where ε e (0; 10 ' ¹ ], where ε e (10 ⁵ ; 10' ² ], then the value is changed to the value determined according to the formula: Θ = - \ + ε for? <0 θ = \ -ε for #> 0 6. The measurement system according to claim 1 The method of claim 1, characterized in that the auxiliary parameter 0 is calculated according to the Chisine mean formula. 7. The system according to p. 1 or 6, characterized in that the auxiliary parameter Θ is calculated according to the arithmetic mean formula: θ _{ + 6ζ 2 8. The system according to p. The method of claim 1, characterized in that the test track controller (KTP) excites the parameter computation system (UOP) after measuring the first four instantaneous current values and four instantaneous voltage values, and after measuring each successive instantaneous current or voltage value. The system according to p. The method of claim 1 and 8, wherein the converter (ADC) sends digital sampling and processing completion signals, characterized in that the metering controller (KTP) comprises: • digital clock signal generator (CLK), the output of which is connected to the excitation input of the ADC converter measurement, • frequency divider reset at the moment of starting the measurements by a value equal to 2 (DF2B), whose input is connected to the digital signal output of the converter (ADC) informing, that the converter (ADC) has finished sampling, and the output is connected to the multiplexer control input (MUX), • the frequency divider reset at the start of measurements by a value equal to 2 (DF2A), whose input is connected to the digital signal output of one of the memory unit buffers ( X8) from the eight memory unit buffers (Χ1-Χ8) connected in series to the converter (ADC) informing that the measurement value has been stored in the buffer queue, while the output is connected to the digital signal input of the parameter calculation system (UOP) indicating whether the memory unit buffers that hold pia values of this and the seventh measurement (X5 and X7), the instantaneous values of current or voltage are stored, • reset buffer system with a length of 8 (UBR8), reset at the moment of starting the measurements, the input of which is connected to the digital signal output of one of the memory unit buffers (X8) with Eight memory unit buffers (Χ1-Χ8) connected in series to the converter (ADC) informing that the measurement value has been stored in the buffer queue, while the output is connected to the parameter calculation system (UOP) to the input of the digital signal triggering the calculation of parameters, with when the first seven initiation signals come, the buffer (UBR8) does not transmit the excitation signal to the output, but in the case of the eighth After the initialization signals, the buffer (UBR8) forwards an excitation signal to its output. 10. The system according to p. 1 and 8, in which the converter (ADC) sends a digital signal to terminate the processing, but does not send a digital signal about the end of sampling, or the signal is not connected to the measuring line controller (KTP), characterized in that the measuring line controller (KTP) comprises: • a digital clock signal generator (CLK), the output of which is connected to the ADC measurement excitation input, • the frequency divider reset at the moment of starting the measurements by a value equal to 2 (DF2A), whose input is connected to the digital signal output of one of the memory unit buffers ( X8) from eight memory unit buffers connected in series (X1 -X8) connected to the converter (ADC) informing that the measurement value has been stored in the buffer queue, while the output is connected to the multiplexer control input (MUX) and to the digital signal input of the system calculation of parameters (UOP) informing whether the instantaneous values of current or voltage are stored in the buffers of memory units storing the values of the fifth and seventh measurement (X5 and X7), • reset buffer system with a length of 8 (UBR8), whose input is connected to is to the digital signal output of one of the memory unit buffers (X8) of eight series-connected buffers of memory units (X1-X8) connected to the converter (ADC) informing that the measurement value has been stored in the buffer queue, and the output is connected to the parameter calculator (UOP) to the input of the digital signal of the excitation calculating parameters, whereby when the first seven initiation signals arrive, the buffer (UBR8) does not transmit the wake-up signal to the output, while when the eighth and subsequent initiation signals arrive, the buffer (UBR8) transfers the wake-up signal to its output.