PL320022A1 - Computer system - Google Patents

Computer system

Info

Publication number
PL320022A1
PL320022A1 PL95320022A PL32002295A PL320022A1 PL 320022 A1 PL320022 A1 PL 320022A1 PL 95320022 A PL95320022 A PL 95320022A PL 32002295 A PL32002295 A PL 32002295A PL 320022 A1 PL320022 A1 PL 320022A1
Authority
PL
Poland
Prior art keywords
computer system
computer
Prior art date
Application number
PL95320022A
Other languages
English (en)
Inventor
Patrick Maurice Bland
Daniel Raymond Cronin
Richard Gerard Hofmann
Dennis Moeller
Lance Michael Venarchick
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of PL320022A1 publication Critical patent/PL320022A1/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/404Coupling between buses using bus bridges with address mapping
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615Address space extension
    • G06F12/0623Address space extension for memory modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
PL95320022A 1994-11-30 1995-11-27 Computer system PL320022A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US35119194A 1994-11-30 1994-11-30
PCT/GB1995/002744 WO1996017304A1 (en) 1994-11-30 1995-11-27 Bus-to-bus bridge

Publications (1)

Publication Number Publication Date
PL320022A1 true PL320022A1 (en) 1997-09-01

Family

ID=23379952

Family Applications (1)

Application Number Title Priority Date Filing Date
PL95320022A PL320022A1 (en) 1994-11-30 1995-11-27 Computer system

Country Status (8)

Country Link
EP (1) EP0795159A1 (ja)
JP (1) JPH08235105A (ja)
KR (1) KR960018940A (ja)
CN (1) CN1151050A (ja)
BR (1) BR9505209A (ja)
CA (1) CA2160499A1 (ja)
PL (1) PL320022A1 (ja)
WO (1) WO1996017304A1 (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH103447A (ja) * 1996-06-18 1998-01-06 Matsushita Electric Ind Co Ltd バスブリッジ装置
US5857080A (en) * 1996-09-10 1999-01-05 Lsi Logic Corporation Apparatus and method for address translation in bus bridge devices
US6163818A (en) * 1998-08-27 2000-12-19 Xerox Corporation Streaming memory controller for a PCI bus
US6457077B1 (en) * 1999-06-10 2002-09-24 International Business Machines Corporation System for executing a current information transfer request even when current information transfer request exceeds current available capacity of a transit buffer
AU2002328037A1 (en) * 2002-09-23 2004-04-08 Telefonaktiebolaget Lm Ericsson (Publ) Computer system and method for accessing external peripheral devices in a computer system
CN102331978A (zh) * 2011-07-07 2012-01-25 曙光信息产业股份有限公司 一种龙芯刀片大内存地址设备dma控制器访问的实现方法
US8817810B2 (en) * 2012-06-27 2014-08-26 Nxp B.V. Communications apparatus, system and method with error mitigation
US10284247B2 (en) 2013-06-10 2019-05-07 Nxp B.V. System and method for bit processing in a central network component

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4878166A (en) * 1987-12-15 1989-10-31 Advanced Micro Devices, Inc. Direct memory access apparatus and methods for transferring data between buses having different performance characteristics
US5214767A (en) * 1989-02-07 1993-05-25 Compaq Computer Corp. Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes
DE69020212T2 (de) * 1989-04-07 1996-04-04 Tektronix Inc Bus-zu-Bus Schnittstellensystem mit Konvertierung der Verriegelung.

Also Published As

Publication number Publication date
JPH08235105A (ja) 1996-09-13
KR960018940A (ko) 1996-06-17
CA2160499A1 (en) 1996-05-31
WO1996017304A1 (en) 1996-06-06
BR9505209A (pt) 1997-09-16
CN1151050A (zh) 1997-06-04
EP0795159A1 (en) 1997-09-17

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