PL3373146T3 - Obsługa błędów w transakcyjnej pamięci buforowanej - Google Patents

Obsługa błędów w transakcyjnej pamięci buforowanej

Info

Publication number
PL3373146T3
PL3373146T3 PL18165252.0T PL18165252T PL3373146T3 PL 3373146 T3 PL3373146 T3 PL 3373146T3 PL 18165252 T PL18165252 T PL 18165252T PL 3373146 T3 PL3373146 T3 PL 3373146T3
Authority
PL
Poland
Prior art keywords
error handling
buffered memory
transactional
transactional buffered
memory
Prior art date
Application number
PL18165252.0T
Other languages
English (en)
Inventor
Brian S. Morris
Bill Nale
Robert G. Blankenship
Eric L. Hendrickson
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of PL3373146T3 publication Critical patent/PL3373146T3/pl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1608—Error detection by comparing the output signals of redundant hardware
    • G06F11/1625—Error detection by comparing the output signals of redundant hardware in communications, e.g. transmission, interfaces
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1654—Error detection by comparing the output of redundant processing systems where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G06F11/167—Error detection by comparing the memory output
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0079—Formats for control data
    • H04L1/0082—Formats for control data fields explicitly indicating existence of error in data being transmitted, e.g. so that downstream stations can avoid decoding erroneous packet; relays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1835—Buffer management
    • H04L1/1838—Buffer management for semi-reliable protocols, e.g. for less sensitive applications such as streaming video
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L2001/0092—Error control systems characterised by the topology of the transmission link
    • H04L2001/0097—Relays

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Multimedia (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
PL18165252.0T 2014-12-20 2015-11-23 Obsługa błędów w transakcyjnej pamięci buforowanej PL3373146T3 (pl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/578,413 US9632862B2 (en) 2014-12-20 2014-12-20 Error handling in transactional buffered memory

Publications (1)

Publication Number Publication Date
PL3373146T3 true PL3373146T3 (pl) 2026-02-16

Family

ID=56127298

Family Applications (1)

Application Number Title Priority Date Filing Date
PL18165252.0T PL3373146T3 (pl) 2014-12-20 2015-11-23 Obsługa błędów w transakcyjnej pamięci buforowanej

Country Status (6)

Country Link
US (2) US9632862B2 (pl)
EP (2) EP3234778B1 (pl)
CN (2) CN107005371B (pl)
PL (1) PL3373146T3 (pl)
TW (2) TWI605464B (pl)
WO (1) WO2016099813A1 (pl)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9424392B2 (en) 2005-11-26 2016-08-23 Natera, Inc. System and method for cleaning noisy genetic data from target individuals using genetic data from genetically related individuals
US11111544B2 (en) 2005-07-29 2021-09-07 Natera, Inc. System and method for cleaning noisy genetic data and determining chromosome copy number
US11111543B2 (en) 2005-07-29 2021-09-07 Natera, Inc. System and method for cleaning noisy genetic data and determining chromosome copy number
US10179937B2 (en) 2014-04-21 2019-01-15 Natera, Inc. Detecting mutations and ploidy in chromosomal segments
US10316362B2 (en) 2010-05-18 2019-06-11 Natera, Inc. Methods for simultaneous amplification of target loci
US12545960B2 (en) 2010-05-18 2026-02-10 Natera, Inc. Methods for simultaneous amplification of target loci
US11322224B2 (en) 2010-05-18 2022-05-03 Natera, Inc. Methods for non-invasive prenatal ploidy calling
CA2821906C (en) 2010-12-22 2020-08-25 Natera, Inc. Methods for non-invasive prenatal paternity testing
US12492429B2 (en) 2014-04-21 2025-12-09 Natera, Inc. Detecting mutations and ploidy in chromosomal segments
US9632862B2 (en) 2014-12-20 2017-04-25 Intel Corporation Error handling in transactional buffered memory
US10838898B2 (en) * 2017-12-05 2020-11-17 Qualcomm Incorporated Bit-interleaved bi-directional transmissions on a multi-drop bus for time-critical data exchange
TWI671637B (zh) * 2018-04-25 2019-09-11 點序科技股份有限公司 記憶體管理裝置及其操作方法
CN109271108B (zh) * 2018-09-03 2021-11-30 青岛镕铭半导体有限公司 一种存储器控制装置及数据存储设备
CN109508247B (zh) * 2018-11-09 2022-02-11 英业达科技有限公司 定位内存错误发生位置的方法、系统、及电子设备
US10771189B2 (en) * 2018-12-18 2020-09-08 Intel Corporation Forward error correction mechanism for data transmission across multi-lane links
US11637657B2 (en) 2019-02-15 2023-04-25 Intel Corporation Low-latency forward error correction for high-speed serial links
US11249837B2 (en) 2019-03-01 2022-02-15 Intel Corporation Flit-based parallel-forward error correction and parity
US11296994B2 (en) 2019-05-13 2022-04-05 Intel Corporation Ordered sets for high-speed interconnects
US11775470B2 (en) 2019-11-20 2023-10-03 Intel Corporation Transaction layer packet format
US11740958B2 (en) 2019-11-27 2023-08-29 Intel Corporation Multi-protocol support on common physical layer
US11886312B2 (en) * 2020-04-07 2024-01-30 Intel Corporation Characterizing error correlation based on error logging for computer buses
US12155474B2 (en) 2020-07-06 2024-11-26 Intel Corporation Characterizing and margining multi-voltage signal encoding for interconnects
US12056029B2 (en) 2020-07-27 2024-08-06 Intel Corporation In-system validation of interconnects by error injection and measurement
US11296995B2 (en) 2020-08-31 2022-04-05 Micron Technology, Inc. Reduced sized encoding of packet length field
US11360920B2 (en) 2020-08-31 2022-06-14 Micron Technology, Inc. Mapping high-speed, point-to-point interface channels to packet virtual channels
US11412075B2 (en) * 2020-08-31 2022-08-09 Micron Technology, Inc. Multiple protocol header processing
US11539623B2 (en) 2020-08-31 2022-12-27 Micron Technology, Inc. Single field for encoding multiple elements
US11418455B2 (en) 2020-08-31 2022-08-16 Micron Technology, Inc. Transparent packet splitting and recombining
US12189470B2 (en) 2020-09-18 2025-01-07 Intel Corporation Forward error correction and cyclic redundancy check mechanisms for latency-critical coherency and memory interconnects
US12316446B2 (en) * 2021-12-20 2025-05-27 Intel Corporation Latency optimization in partial width link states

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5165023A (en) * 1986-12-17 1992-11-17 Massachusetts Institute Of Technology Parallel processing system with processor array and network communications system for transmitting messages of variable length
US6370621B1 (en) 1998-12-21 2002-04-09 Advanced Micro Devices, Inc. Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation
US6493843B1 (en) * 1999-10-28 2002-12-10 Hewlett-Packard Company Chipkill for a low end server or workstation
US7818646B1 (en) * 2003-11-12 2010-10-19 Hewlett-Packard Development Company, L.P. Expectation based event verification
US7734980B2 (en) 2005-06-24 2010-06-08 Intel Corporation Mitigating silent data corruption in a buffered memory module architecture
US7809903B2 (en) * 2005-12-15 2010-10-05 Intel Corporation Coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions
US7562285B2 (en) 2006-01-11 2009-07-14 Rambus Inc. Unidirectional error code transfer for a bidirectional data link
US8127309B1 (en) * 2006-11-10 2012-02-28 Marvell International Ltd. Secure digital input/output interface system
US7949931B2 (en) * 2007-01-02 2011-05-24 International Business Machines Corporation Systems and methods for error detection in a memory system
JP5035176B2 (ja) * 2008-08-21 2012-09-26 富士通株式会社 伝送システム、伝送装置および伝送方法
US8250435B2 (en) 2009-09-15 2012-08-21 Intel Corporation Memory error detection and/or correction
CN101673255B (zh) * 2009-10-21 2012-07-11 威盛电子股份有限公司 通用串行总线主机控制器和通用串行总线主机控制方法
US10430298B2 (en) * 2010-10-28 2019-10-01 Microsoft Technology Licensing, Llc Versatile in-memory database recovery using logical log records
CN102480346B (zh) * 2010-11-26 2014-12-10 中国科学院声学研究所 一种网络数据可靠传输方法
US8677027B2 (en) * 2011-06-01 2014-03-18 International Business Machines Corporation Fibre channel input/output data routing system and method
US9037907B2 (en) * 2011-06-10 2015-05-19 International Business Machines Corporation Operator message commands for testing a coupling facility
CN103141050B (zh) * 2011-12-28 2014-11-05 华为技术有限公司 快速通道互联系统中数据包重传方法、节点
CN102629898B (zh) * 2012-04-11 2014-12-10 华为技术有限公司 数据传输方法、设备及系统
US9507746B2 (en) * 2012-10-22 2016-11-29 Intel Corporation Control messaging in multislot link layer flit
US9479196B2 (en) * 2012-10-22 2016-10-25 Intel Corporation High performance interconnect link layer
KR101691756B1 (ko) * 2012-10-22 2016-12-30 인텔 코포레이션 코히어런스 프로토콜 테이블
US8990640B2 (en) 2012-11-16 2015-03-24 International Business Machines Corporation Selective posted data error detection based on request type
US9298525B2 (en) * 2012-12-04 2016-03-29 Accenture Global Services Limited Adaptive fault diagnosis
JP5793690B2 (ja) * 2012-12-28 2015-10-14 パナソニックＩｐマネジメント株式会社 インタフェース装置、およびメモリバスシステム
US9176799B2 (en) * 2012-12-31 2015-11-03 Advanced Micro Devices, Inc. Hop-by-hop error detection in a server system
US9632862B2 (en) 2014-12-20 2017-04-25 Intel Corporation Error handling in transactional buffered memory

Also Published As

Publication number Publication date
CN107005371B (zh) 2021-10-15
CN108363637A (zh) 2018-08-03
TW201631600A (zh) 2016-09-01
US10360096B2 (en) 2019-07-23
EP3234778A4 (en) 2018-08-22
US9632862B2 (en) 2017-04-25
EP3373146A1 (en) 2018-09-12
EP3234778A1 (en) 2017-10-25
TW201824294A (zh) 2018-07-01
US20170322841A1 (en) 2017-11-09
TWI671751B (zh) 2019-09-11
TWI605464B (zh) 2017-11-11
EP3373146B1 (en) 2025-09-17
US20160179610A1 (en) 2016-06-23
WO2016099813A1 (en) 2016-06-23
EP3234778B1 (en) 2023-08-09
CN107005371A (zh) 2017-08-01

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