PL3382533T3 - Hierarchiczny plik rejestru dla gpgpu - Google Patents

Hierarchiczny plik rejestru dla gpgpu

Info

Publication number
PL3382533T3
PL3382533T3 PL18160823.3T PL18160823T PL3382533T3 PL 3382533 T3 PL3382533 T3 PL 3382533T3 PL 18160823 T PL18160823 T PL 18160823T PL 3382533 T3 PL3382533 T3 PL 3382533T3
Authority
PL
Poland
Prior art keywords
gpgpu
register file
hierarchical register
hierarchical
file
Prior art date
Application number
PL18160823.3T
Other languages
English (en)
Inventor
Abhishek R. APPU
Altug Koker
Joydeep RAY
Kamal SINHA
Kiran C. Veernapu
Subramaniam Maiyuran
Prasoonkumar Surti
Guei-Yuan Lueh
David Puffer
Supratim PAL
Eric J. Hoekstra
Travis T. Schluessler
Linda L. Hurd
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of PL3382533T3 publication Critical patent/PL3382533T3/pl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
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    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
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    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
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    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
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    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
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    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
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    • G06F9/00—Arrangements for program control, e.g. control units
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
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    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
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    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—Three-dimensional [3D] image rendering
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2210/00—Indexing scheme for image generation or computer graphics
    • G06T2210/12—Bounding box
    • G—PHYSICS
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    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2210/00—Indexing scheme for image generation or computer graphics
    • G06T2210/52—Parallel processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Image Processing (AREA)
  • Image Generation (AREA)
  • Debugging And Monitoring (AREA)
PL18160823.3T 2017-04-01 2018-03-08 Hierarchiczny plik rejestru dla gpgpu PL3382533T3 (pl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/477,033 US10423415B2 (en) 2017-04-01 2017-04-01 Hierarchical general register file (GRF) for execution block

Publications (1)

Publication Number Publication Date
PL3382533T3 true PL3382533T3 (pl) 2023-01-16

Family

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Family Applications (1)

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PL18160823.3T PL3382533T3 (pl) 2017-04-01 2018-03-08 Hierarchiczny plik rejestru dla gpgpu

Country Status (5)

Country Link
US (3) US10423415B2 (pl)
EP (1) EP3382533B1 (pl)
CN (2) CN119006265A (pl)
ES (1) ES2929978T3 (pl)
PL (1) PL3382533T3 (pl)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10423415B2 (en) 2017-04-01 2019-09-24 Intel Corporation Hierarchical general register file (GRF) for execution block
US10649956B2 (en) 2017-04-01 2020-05-12 Intel Corporation Engine to enable high speed context switching via on-die storage
US10241921B2 (en) * 2017-04-17 2019-03-26 Intel Corporation Avoid cache lookup for cold cache
US10409614B2 (en) 2017-04-24 2019-09-10 Intel Corporation Instructions having support for floating point and integer data types in the same register
US10474458B2 (en) 2017-04-28 2019-11-12 Intel Corporation Instructions and logic to perform floating-point and integer operations for machine learning
US10880163B2 (en) * 2019-01-31 2020-12-29 Dell Products, L.P. System and method for hardware management and configuration in a datacenter using augmented reality and available sensor data
WO2020190776A1 (en) * 2019-03-15 2020-09-24 Intel Corporation Synchronizing encrypted workloads across multiple graphics processing units
PL3938914T3 (pl) 2019-03-15 2025-03-31 Intel Corporation Dynamiczna rekonfiguracja pamięci
WO2020190807A1 (en) 2019-03-15 2020-09-24 Intel Corporation Systolic disaggregation within a matrix accelerator architecture
US12182035B2 (en) 2019-03-15 2024-12-31 Intel Corporation Systems and methods for cache optimization
US11934342B2 (en) 2019-03-15 2024-03-19 Intel Corporation Assistance for hardware prefetch in cache access
US11782713B1 (en) * 2019-08-27 2023-10-10 Amazon Technologies, Inc. Security vulnerability mitigation using address space co-execution
US11663746B2 (en) 2019-11-15 2023-05-30 Intel Corporation Systolic arithmetic on sparse data
US11861761B2 (en) 2019-11-15 2024-01-02 Intel Corporation Graphics processing unit processing and caching improvements
US11630667B2 (en) * 2019-11-27 2023-04-18 Advanced Micro Devices, Inc. Dedicated vector sub-processor system
US11204765B1 (en) * 2020-08-26 2021-12-21 Qualcomm Incorporated Deferred GPR allocation for texture/load instruction block
US11669401B2 (en) * 2020-08-28 2023-06-06 Micron Technology, Inc. Status register power interruption protection
CN112181493B (zh) * 2020-09-24 2022-09-13 成都海光集成电路设计有限公司 寄存器网络架构和寄存器访问方法
US11314508B1 (en) * 2021-02-01 2022-04-26 National Technology & Engineering Solutions Of Sandia, Llc FPGA-based computing system for processing data in size, weight, and power constrained environments
US12164952B2 (en) * 2021-06-25 2024-12-10 Intel Corporation Barrier state save and restore for preemption in a graphics environment
US12210905B2 (en) 2021-06-25 2025-01-28 Intel Corporation Multiple register allocation sizes for threads
US11775310B2 (en) * 2021-11-16 2023-10-03 Nxp B.V. Data processing system having distrubuted registers
US11977496B1 (en) 2022-09-29 2024-05-07 Amazon Technologies, Inc. Security vulnerability mitigation using hardware-supported context-dependent address space hiding
US12147542B1 (en) * 2024-01-25 2024-11-19 Parry Labs, Llc Field-deployable hardware apparatus

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5165038A (en) * 1989-12-29 1992-11-17 Supercomputer Systems Limited Partnership Global registers for a multiprocessor system
US6345354B1 (en) * 1999-04-29 2002-02-05 Mips Technologies, Inc. Register file access
JP2004220070A (ja) * 2003-01-09 2004-08-05 Japan Science & Technology Agency コンテキスト切り替え方法及び装置、中央演算装置、コンテキスト切り替えプログラム及びそれを記憶したコンピュータ読み取り可能な記憶媒体
US20050204118A1 (en) * 2004-02-27 2005-09-15 National Chiao Tung University Method for inter-cluster communication that employs register permutation
US7873812B1 (en) 2004-04-05 2011-01-18 Tibet MIMAR Method and system for efficient matrix multiplication in a SIMD processor architecture
US7284092B2 (en) * 2004-06-24 2007-10-16 International Business Machines Corporation Digital data processing apparatus having multi-level register file
BRPI0519243A2 (pt) * 2004-12-22 2009-01-06 Neurochem Int Ltd mÉtodos e composiÇÕes para tratar doenÇas relacionadas a amilàide
US20060230257A1 (en) * 2005-04-11 2006-10-12 Muhammad Ahmed System and method of using a predicate value to access a register file
US20070083735A1 (en) * 2005-08-29 2007-04-12 Glew Andrew F Hierarchical processor
US8296550B2 (en) 2005-08-29 2012-10-23 The Invention Science Fund I, Llc Hierarchical register file with operand capture ports
DE112006004005T5 (de) * 2006-10-27 2009-06-10 Intel Corporation, Santa Clara Kommunikation zwischen Mehrfach-Ausführungsfolgen in einem Prozessor
US8108625B1 (en) * 2006-10-30 2012-01-31 Nvidia Corporation Shared memory with parallel access and access conflict resolution mechanism
US8533681B2 (en) * 2007-03-07 2013-09-10 The Board Of Trustees Of The University Of Illinois Atomicity violation detection using access interleaving invariants
US20090063881A1 (en) * 2007-08-31 2009-03-05 Mips Technologies, Inc. Low-overhead/power-saving processor synchronization mechanism, and applications thereof
US8200949B1 (en) 2008-12-09 2012-06-12 Nvidia Corporation Policy based allocation of register file cache to threads in multi-threaded processor
US20110016158A1 (en) * 2009-07-16 2011-01-20 Gilles Robert Vergnory-Mion Generation of dimensional metadata based on rdbms data
US8533435B2 (en) 2009-09-24 2013-09-10 Nvidia Corporation Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict
US8458446B2 (en) * 2009-09-30 2013-06-04 Oracle America, Inc. Accessing a multibank register file using a thread identifier
KR101636377B1 (ko) * 2009-10-23 2016-07-06 삼성전자주식회사 재구성 프로세서, 재구성 제어 장치 및 방법, 그리고, 스레드 모델링 방법
US9367462B2 (en) * 2009-12-29 2016-06-14 Empire Technology Development Llc Shared memories for energy efficient multi-core processors
US8732711B2 (en) * 2010-09-24 2014-05-20 Nvidia Corporation Two-level scheduler for multi-threaded processing
US8539462B2 (en) * 2010-12-21 2013-09-17 National Tsing Hua University Method for allocating registers for a processor based on cycle information
CN103186502B (zh) * 2011-12-30 2016-08-10 世意法（北京）半导体研发有限责任公司 用于共享处理器过程上下文的寄存器堆组织
US10169091B2 (en) * 2012-10-25 2019-01-01 Nvidia Corporation Efficient memory virtualization in multi-threaded processing units
US9229717B2 (en) * 2012-12-11 2016-01-05 Nvidia Corporation Register allocation for clustered multi-level register files
GB2501791B (en) * 2013-01-24 2014-06-11 Imagination Tech Ltd Register file having a plurality of sub-register files
CN103412828B (zh) * 2013-08-13 2016-12-28 华为技术有限公司 一种数据处理的方法和设备
US10223333B2 (en) 2014-08-29 2019-03-05 Nvidia Corporation Performing multi-convolution operations in a parallel processing system
CN105045652B (zh) * 2015-07-07 2018-11-13 深圳市云舒网络技术有限公司 一种多终端共同处理多并行线程程序的方法和处理系统
US20170060593A1 (en) * 2015-09-02 2017-03-02 Qualcomm Incorporated Hierarchical register file system
US10853904B2 (en) 2016-03-24 2020-12-01 Advanced Micro Devices, Inc. Hierarchical register file at a graphics processing unit
US10997496B2 (en) 2016-08-11 2021-05-04 Nvidia Corporation Sparse convolutional neural network accelerator
US10891538B2 (en) 2016-08-11 2021-01-12 Nvidia Corporation Sparse convolutional neural network accelerator
US10423415B2 (en) 2017-04-01 2019-09-24 Intel Corporation Hierarchical general register file (GRF) for execution block

Also Published As

Publication number Publication date
US20180285106A1 (en) 2018-10-04
US10423415B2 (en) 2019-09-24
US20210349715A1 (en) 2021-11-11
CN119006265A (zh) 2024-11-22
EP3382533A1 (en) 2018-10-03
CN108694698A (zh) 2018-10-23
ES2929978T3 (es) 2022-12-05
US11010163B2 (en) 2021-05-18
CN108694698B (zh) 2024-09-03
EP3382533B1 (en) 2022-09-14
US20200026514A1 (en) 2020-01-23
US11507375B2 (en) 2022-11-22

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