PL3579117T3 - Instrukcja mnożenia macierzy o zmiennym formacie i zmiennej rzadkości - Google Patents

Instrukcja mnożenia macierzy o zmiennym formacie i zmiennej rzadkości

Info

Publication number
PL3579117T3
PL3579117T3 PL19172622.3T PL19172622T PL3579117T3 PL 3579117 T3 PL3579117 T3 PL 3579117T3 PL 19172622 T PL19172622 T PL 19172622T PL 3579117 T3 PL3579117 T3 PL 3579117T3
Authority
PL
Poland
Prior art keywords
variable
sparseness
format
matrix multiplication
multiplication instruction
Prior art date
Application number
PL19172622.3T
Other languages
English (en)
Inventor
Mark A. Anders
Himanshu Kaul
Sanu Mathew
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of PL3579117T3 publication Critical patent/PL3579117T3/pl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Biophysics (AREA)
  • Biomedical Technology (AREA)
  • Evolutionary Computation (AREA)
  • Artificial Intelligence (AREA)
  • Databases & Information Systems (AREA)
  • Algebra (AREA)
  • Neurology (AREA)
  • Computational Linguistics (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Medical Informatics (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Multi Processors (AREA)
  • Complex Calculations (AREA)
PL19172622.3T 2018-06-08 2019-05-03 Instrukcja mnożenia macierzy o zmiennym formacie i zmiennej rzadkości PL3579117T3 (pl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16/003,545 US10599429B2 (en) 2018-06-08 2018-06-08 Variable format, variable sparsity matrix multiplication instruction

Publications (1)

Publication Number Publication Date
PL3579117T3 true PL3579117T3 (pl) 2024-09-23

Family

ID=65229501

Family Applications (1)

Application Number Title Priority Date Filing Date
PL19172622.3T PL3579117T3 (pl) 2018-06-08 2019-05-03 Instrukcja mnożenia macierzy o zmiennym formacie i zmiennej rzadkości

Country Status (5)

Country Link
US (2) US10599429B2 (pl)
EP (2) EP3772000A1 (pl)
CN (3) CN119166216A (pl)
ES (1) ES2988859T3 (pl)
PL (1) PL3579117T3 (pl)

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US20210200711A1 (en) * 2019-12-28 2021-07-01 Intel Corporation System and Method for Configurable Systolic Array with Partial Read/Write
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US11614920B2 (en) * 2020-05-07 2023-03-28 Meta Platforms, Inc. Bypassing zero-value multiplications in a hardware multiplier
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KR102724444B1 (ko) * 2020-07-10 2024-11-01 삼성전자주식회사 전자 장치 및 그의 제어 방법
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Also Published As

Publication number Publication date
US10599429B2 (en) 2020-03-24
US20190042250A1 (en) 2019-02-07
CN110580175A (zh) 2019-12-17
EP3772000A1 (en) 2021-02-03
EP3579117B1 (en) 2024-05-29
CN112099852A (zh) 2020-12-18
EP3579117A1 (en) 2019-12-11
US20200334038A1 (en) 2020-10-22
ES2988859T3 (es) 2024-11-21
CN112099852B (zh) 2024-08-30
CN119166216A (zh) 2024-12-20

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