PL3719659T3 - Sposób, aparat i system do pomiaru opóźnienia w fizycznej jednostce obwodu - Google Patents

Sposób, aparat i system do pomiaru opóźnienia w fizycznej jednostce obwodu

Info

Publication number
PL3719659T3
PL3719659T3 PL20175936.2T PL20175936T PL3719659T3 PL 3719659 T3 PL3719659 T3 PL 3719659T3 PL 20175936 T PL20175936 T PL 20175936T PL 3719659 T3 PL3719659 T3 PL 3719659T3
Authority
PL
Poland
Prior art keywords
circuit
physical unit
measuring latency
latency
measuring
Prior art date
Application number
PL20175936.2T
Other languages
English (en)
Inventor
David Harriman
Mahesh Wagh
Abdul Ismail
Daniel Froelich
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of PL3719659T3 publication Critical patent/PL3719659T3/pl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H04L43/0858—One way delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
    • H04L43/106—Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Health & Medical Sciences (AREA)
  • Cardiology (AREA)
  • General Health & Medical Sciences (AREA)
  • Environmental & Geological Engineering (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Information Transfer Systems (AREA)
  • Measuring Frequencies, Analyzing Spectra (AREA)
  • Advance Control (AREA)
PL20175936.2T 2013-10-30 2013-10-30 Sposób, aparat i system do pomiaru opóźnienia w fizycznej jednostce obwodu PL3719659T3 (pl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP20175936.2A EP3719659B1 (en) 2013-10-30 2013-10-30 A method, apparatus and system for measuring latency in a physical unit of a circuit
PCT/US2013/067396 WO2015065349A1 (en) 2013-10-30 2013-10-30 A method, apparatus and system for measuring latency in a physical unit of a circuit

Publications (1)

Publication Number Publication Date
PL3719659T3 true PL3719659T3 (pl) 2024-04-08

Family

ID=52995426

Family Applications (2)

Application Number Title Priority Date Filing Date
PL20175936.2T PL3719659T3 (pl) 2013-10-30 2013-10-30 Sposób, aparat i system do pomiaru opóźnienia w fizycznej jednostce obwodu
PL23193275.7T PL4254209T3 (pl) 2013-10-30 2013-10-30 Sposób, aparat i system do pomiaru opóźnienia w fizycznej jednostce obwodu

Family Applications After (1)

Application Number Title Priority Date Filing Date
PL23193275.7T PL4254209T3 (pl) 2013-10-30 2013-10-30 Sposób, aparat i system do pomiaru opóźnienia w fizycznej jednostce obwodu

Country Status (6)

Country Link
US (2) US9262347B2 (pl)
EP (3) EP3719659B1 (pl)
KR (2) KR101974323B1 (pl)
CN (2) CN105593830B (pl)
PL (2) PL3719659T3 (pl)
WO (1) WO2015065349A1 (pl)

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US10198394B2 (en) * 2016-05-24 2019-02-05 Intel Corporation Reduced pin count interface
CN106686627B (zh) * 2016-12-07 2020-01-14 Oppo广东移动通信有限公司 WiFi/热点的开启方法及装置
US10372657B2 (en) * 2016-12-26 2019-08-06 Intel Corporation Bimodal PHY for low latency in high speed interconnects
US10649486B1 (en) * 2016-12-28 2020-05-12 Intel Corporation Apparatus and methods for accurate latency measurements in integrated circuits
US11809353B2 (en) * 2017-03-31 2023-11-07 Intel Corporation Component firmware interaction using hardware registers
US10860449B2 (en) * 2017-03-31 2020-12-08 Intel Corporation Adjustable retimer buffer
US10437763B2 (en) * 2017-04-07 2019-10-08 Nxp B.V. Method and device for universal serial bus (USB) communication
US11249808B2 (en) 2017-08-22 2022-02-15 Intel Corporation Connecting accelerator resources using a switch
US10887196B2 (en) * 2018-11-28 2021-01-05 Microsoft Technology Licensing, Llc Efficient metric calculation with recursive data processing
US11343748B2 (en) * 2019-02-08 2022-05-24 Samsung Electronics Co., Ltd. Coordinated beam selection in cellular mesh network
US10581587B1 (en) * 2019-04-29 2020-03-03 Advanced Micro Devices, Inc. Deskewing method for a physical layer interface on a multi-chip module
US11151011B2 (en) 2019-10-01 2021-10-19 International Business Machines Corporation Uncore input/output latency analysis
CN112988653B (zh) * 2019-12-16 2024-04-12 广州希姆半导体科技有限公司 数据处理电路、装置以及方法
US11271712B2 (en) * 2020-01-07 2022-03-08 Microchip Technology Inc. Daisy-chained synchronous ethernet clock recovery
US11832198B2 (en) * 2020-07-02 2023-11-28 Qualcomm Incorporated Cell synchronization in physical (PHY) layer and medium access control (MAC) layer mobility
CN113220231B (zh) * 2021-05-11 2022-07-22 无锡众星微系统技术有限公司 一种支持stp应用的自适应流控方法与装置
US11474969B1 (en) * 2021-05-12 2022-10-18 Gowin Semiconductor Corporation Methods and apparatus for providing a serializer and deserializer (SERDES) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)
US11843376B2 (en) 2021-05-12 2023-12-12 Gowin Semiconductor Corporation Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA)
CN113608574B (zh) * 2021-08-09 2024-06-11 贵州省计量测试院 一种计算机微秒级时间输出方法、系统及校准系统
CN118432753A (zh) * 2023-02-02 2024-08-02 微芯片技术股份有限公司 确定在物理层处的延迟

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Also Published As

Publication number Publication date
EP4254209A2 (en) 2023-10-04
EP3063640A4 (en) 2017-06-07
EP3063640A1 (en) 2016-09-07
CN105593830B (zh) 2019-04-09
KR20160048191A (ko) 2016-05-03
KR101974323B1 (ko) 2019-04-30
EP4254209B1 (en) 2025-11-12
PL4254209T3 (pl) 2026-03-23
CN108595355B (zh) 2021-05-25
US9262347B2 (en) 2016-02-16
EP4254209A3 (en) 2023-11-22
EP3063640B1 (en) 2020-10-07
US20160124894A1 (en) 2016-05-05
CN105593830A (zh) 2016-05-18
KR101855603B1 (ko) 2018-06-08
US9558145B2 (en) 2017-01-31
EP3719659A1 (en) 2020-10-07
KR20180041257A (ko) 2018-04-23
WO2015065349A1 (en) 2015-05-07
EP3719659B1 (en) 2023-10-04
US20150117504A1 (en) 2015-04-30
CN108595355A (zh) 2018-09-28
EP3719659C0 (en) 2023-10-04

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