PL423627A1 - System for generation of a pulse string with controlled time relations - Google Patents

System for generation of a pulse string with controlled time relations

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Publication number
PL423627A1
PL423627A1 PL423627A PL42362717A PL423627A1 PL 423627 A1 PL423627 A1 PL 423627A1 PL 423627 A PL423627 A PL 423627A PL 42362717 A PL42362717 A PL 42362717A PL 423627 A1 PL423627 A1 PL 423627A1
Authority
PL
Poland
Prior art keywords
multiplexers
input
generation
register
output
Prior art date
Application number
PL423627A
Other languages
Polish (pl)
Other versions
PL233271B1 (en
Inventor
Paweł Kwiatkowski
Original Assignee
Wojskowa Akademia Techniczna Im Jaroslawa Dabrowskiego
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wojskowa Akademia Techniczna Im Jaroslawa Dabrowskiego filed Critical Wojskowa Akademia Techniczna Im Jaroslawa Dabrowskiego
Priority to PL423627A priority Critical patent/PL233271B1/en
Publication of PL423627A1 publication Critical patent/PL423627A1/en
Publication of PL233271B1 publication Critical patent/PL233271B1/en

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  • Time-Division Multiplex Systems (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Pulse Circuits (AREA)

Abstract

Układ przetwornika cyfra-czas, składa się z elektronicznego rejestru z wyjściem równoległym (1), linii opóźniającej (2) zbudowanej z szeregowo połączonych multiplekserów (3a-3n) oraz sieci dystrybucji sygnału o stałym opóźnieniu (4). Multipleksery (3a-3n) posiadają trzy wejścia - dwa informacyjne (5, 6) i jedno sterujące (8) oraz jedno wyjście (7). Wejście informacyjne (5) multiplekserów (3a, 3n) jest dołączone do rejestru (1) a wejście informacyjne (6) multipleksera (3a) może być dołączone do rejestru (1) bądź masy, bądź zasilania układu. Wejście informacyjne (6) multipleksów (3n) jest dołączone do wyjścia (7) poprzedniego multipleksera w linii opóźniającej (2). Wejście adresowe (8) multiplekserów (3a, 3n) jest dołączone do sygnału wejściowego (WE), sygnał wejściowy (WE) jest dołączony do wszystkich wejść adresowych (8) poprzez sieć dystrybucji sygnału o stałym opóźnieniu (4).The digital-time converter system consists of an electronic register with a parallel output (1), a delay line (2) built of serially connected multiplexers (3a-3n) and a constant delay signal distribution network (4). Multiplexers (3a-3n) have three inputs - two information (5, 6) and one control (8) and one output (7). The information input (5) of the multiplexers (3a, 3n) is attached to the register (1) and the information input (6) of the multiplexer (3a) can be connected to the register (1) of either the ground or the system power supply. The information input (6) of the multiplexes (3n) is connected to the output (7) of the previous multiplexer in the delay line (2). The address input (8) of the multiplexers (3a, 3n) is connected to the input signal (EC), the input signal (EC) is connected to all address inputs (8) through a constant delay signal distribution network (4).

PL423627A 2017-11-28 2017-11-28 System for generation of a pulse string with controlled time relations PL233271B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PL423627A PL233271B1 (en) 2017-11-28 2017-11-28 System for generation of a pulse string with controlled time relations

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PL423627A PL233271B1 (en) 2017-11-28 2017-11-28 System for generation of a pulse string with controlled time relations

Publications (2)

Publication Number Publication Date
PL423627A1 true PL423627A1 (en) 2019-06-03
PL233271B1 PL233271B1 (en) 2019-09-30

Family

ID=66649234

Family Applications (1)

Application Number Title Priority Date Filing Date
PL423627A PL233271B1 (en) 2017-11-28 2017-11-28 System for generation of a pulse string with controlled time relations

Country Status (1)

Country Link
PL (1) PL233271B1 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63123229A (en) * 1986-11-12 1988-05-27 Nec Corp Digital-analog converter
JPH06232754A (en) * 1992-12-16 1994-08-19 Philips Electron Nv Analog/digital converter
US5764165A (en) * 1996-05-03 1998-06-09 Quantum Corporation Rotated counter bit pulse width modulated digital to analog converter
EP0932257A2 (en) * 1998-01-27 1999-07-28 Matsushita Electric Industrial Co., Ltd. Digital-to-analog converter and digital-to-analog converting method
KR20030062480A (en) * 2002-01-17 2003-07-28 삼성전자주식회사 Delay-Locked Loop using Digital-to-Analog Converter controlled by Successive Approximation Register
US20110156789A1 (en) * 2009-12-29 2011-06-30 Stmicroelectronics S.R.I. Control system for a phase generator and corresponding control method
TW201415810A (en) * 2012-10-11 2014-04-16 Tritan Technology Inc Apparatus for differential interpolation pulse width modulation digital-to-analog conversion and output signal

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63123229A (en) * 1986-11-12 1988-05-27 Nec Corp Digital-analog converter
JPH06232754A (en) * 1992-12-16 1994-08-19 Philips Electron Nv Analog/digital converter
US5764165A (en) * 1996-05-03 1998-06-09 Quantum Corporation Rotated counter bit pulse width modulated digital to analog converter
EP0932257A2 (en) * 1998-01-27 1999-07-28 Matsushita Electric Industrial Co., Ltd. Digital-to-analog converter and digital-to-analog converting method
KR20030062480A (en) * 2002-01-17 2003-07-28 삼성전자주식회사 Delay-Locked Loop using Digital-to-Analog Converter controlled by Successive Approximation Register
US20110156789A1 (en) * 2009-12-29 2011-06-30 Stmicroelectronics S.R.I. Control system for a phase generator and corresponding control method
TW201415810A (en) * 2012-10-11 2014-04-16 Tritan Technology Inc Apparatus for differential interpolation pulse width modulation digital-to-analog conversion and output signal

Also Published As

Publication number Publication date
PL233271B1 (en) 2019-09-30

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