PL446725A1 - Ohmic contact for GaN-based semiconductor structures and method of producing said contact - Google Patents

Ohmic contact for GaN-based semiconductor structures and method of producing said contact

Info

Publication number
PL446725A1
PL446725A1 PL446725A PL44672523A PL446725A1 PL 446725 A1 PL446725 A1 PL 446725A1 PL 446725 A PL446725 A PL 446725A PL 44672523 A PL44672523 A PL 44672523A PL 446725 A1 PL446725 A1 PL 446725A1
Authority
PL
Poland
Prior art keywords
layer
contact
thick
gan
producing
Prior art date
Application number
PL446725A
Other languages
Polish (pl)
Inventor
Oskar Sadowski
Andrzej Taube
Anna Szerling
Maciej Kamiński
Original Assignee
Sieć Badawcza Łukasiewicz - Instytut Mikroelektroniki I Fotoniki
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sieć Badawcza Łukasiewicz - Instytut Mikroelektroniki I Fotoniki filed Critical Sieć Badawcza Łukasiewicz - Instytut Mikroelektroniki I Fotoniki
Priority to PL446725A priority Critical patent/PL446725A1/en
Publication of PL446725A1 publication Critical patent/PL446725A1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0114—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors to diamond, semiconducting diamond-like carbon or graphene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0116—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group III-V semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1404—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
    • H10P32/1406—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/051—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

Przedmiotem zgłoszenia jest kontakt omowy dla struktur półprzewodnikowych na bazie GaN oraz sposób wytwarzania tego kontaktu. Kontakt ten jest przeznaczony do stosowania w wertykalnych przyrządach mocy, takich jak dioda p-i-n, dioda Schottky'ego oraz wertykalny tranzystor typu MOSFET, od których wymagana jest duża niezawodność. Kontakt ten bezpośrednio na stronie polarności azotowej podłoża GaN (1) ma warstwę Ti (2) o grubości 10 - 50 nm, oraz warstwę Al (3) o grubości 40 – 250 nm, odpowiadające za niską wartość bariery Schottky'ego na złączu metal-półprzewodnik. Na warstwie (3) znajduje się warstwa TiN (4) o grubości 10 — 50 nm, a na niej warstwa Au (5) o grubości 20 - 100 nm, które to warstwy obniżają rezystancję kontaktu. W sposobie, po odpowiednim przygotowaniu powierzchni o polarności azotowej podłoża GaN za pomocą magnetronowego rozpylania katodowego, osadza się najpierw warstwę Ti, na niej warstwę Al, na warstwie Al warstwę TiN, a na warstwie TiN osadza się warstwę Au.The subject of the application is an ohmic contact for semiconductor structures based on GaN and a method of producing this contact. This contact is intended for use in vertical power devices, such as a p-i-n diode, a Schottky diode and a vertical MOSFET transistor, which require high reliability. This contact directly on the nitrogen polarity side of the GaN substrate (1) has a Ti layer (2) 10 - 50 nm thick, and an Al layer (3) 40 - 250 nm thick, responsible for the low value of the Schottky barrier at the metal-semiconductor junction. On the layer (3) there is a TiN layer (4) 10 - 50 nm thick, and on it a Au layer (5) 20 - 100 nm thick, which layers reduce the contact resistance. In the method, after appropriate preparation of the nitrogen polar surface of the GaN substrate by magnetron sputtering, a Ti layer is first deposited, an Al layer thereon, a TiN layer on the Al layer, and an Au layer on the TiN layer.

PL446725A 2023-11-13 2023-11-13 Ohmic contact for GaN-based semiconductor structures and method of producing said contact PL446725A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PL446725A PL446725A1 (en) 2023-11-13 2023-11-13 Ohmic contact for GaN-based semiconductor structures and method of producing said contact

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PL446725A PL446725A1 (en) 2023-11-13 2023-11-13 Ohmic contact for GaN-based semiconductor structures and method of producing said contact

Publications (1)

Publication Number Publication Date
PL446725A1 true PL446725A1 (en) 2025-05-19

Family

ID=95713441

Family Applications (1)

Application Number Title Priority Date Filing Date
PL446725A PL446725A1 (en) 2023-11-13 2023-11-13 Ohmic contact for GaN-based semiconductor structures and method of producing said contact

Country Status (1)

Country Link
PL (1) PL446725A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013021016A (en) * 2011-07-07 2013-01-31 Sharp Corp GaN-BASED SEMICONDUCTOR ELEMENT MANUFACTURING METHOD
AU2021209190A1 (en) * 2017-03-08 2021-08-19 Raytheon Company Schottky contact structure for semiconductor devices and method for forming such schottky contact structure
WO2022103133A1 (en) * 2020-11-13 2022-05-19 한국원자력연구원 Method for forming ohmic contact of gan-based electronic device, and ohmic contact of gan-based electronic device,manufactured thereby

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013021016A (en) * 2011-07-07 2013-01-31 Sharp Corp GaN-BASED SEMICONDUCTOR ELEMENT MANUFACTURING METHOD
AU2021209190A1 (en) * 2017-03-08 2021-08-19 Raytheon Company Schottky contact structure for semiconductor devices and method for forming such schottky contact structure
WO2022103133A1 (en) * 2020-11-13 2022-05-19 한국원자력연구원 Method for forming ohmic contact of gan-based electronic device, and ohmic contact of gan-based electronic device,manufactured thereby

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