PL450809A3 - Random generator with metastability circuit - Google Patents
Random generator with metastability circuitInfo
- Publication number
- PL450809A3 PL450809A3 PL450809A PL45080924A PL450809A3 PL 450809 A3 PL450809 A3 PL 450809A3 PL 450809 A PL450809 A PL 450809A PL 45080924 A PL45080924 A PL 45080924A PL 450809 A3 PL450809 A3 PL 450809A3
- Authority
- PL
- Poland
- Prior art keywords
- flip
- flop
- circuit
- metastability
- inputs
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
Abstract
Zgłoszenie dotyczy układu metastabilnościowego (UM) generatora losowego i sposobu regulacji pracą tego układu, zbudowanego z przerzutnika (P), którego wejścia i wyjście (D, C, Q) stanowią wejścia i wyjście układu metastabilnościowego (i1-UM, i2-UM, o-UM). Istotą układu metastabilnościowego jest specjalna budowa przerzutnika posiadająca układy opóźniające w obydwu stopniach master i slave oraz szereg wejść (lo1M, lo2M, lo1S, lo2S, lsM, lsS) pozwalających na sterowanie pracą przerzutnika, którą to pracą steruje układ kompensacji i regulacji (UKR), dołączony także do wejść i wyjścia przerzutnika (D, C, Q). Rozwiązanie polega na: regulację pracy między stopniem master i slave przerzutnika, regulowane spowalnianie części master i slave w dużym zakresie, symetryzację pracy każdego stopnia przerzutnika, wzorcowanie układu metastabilnościowego, kompensację w trakcie pracy, czy regulację pobieranej mocy. Możliwa jest kompensacja rozrzutów technologicznych, zmiana położenia i rozmiaru okna metastabilności, ustalenie i regulacja czasu regeneracji przerzutnika, kompensacja wpływu starzenia się i pracy mechanicznej, czy oddziaływania czynników środowiskowych.The application concerns a metastability circuit (UM) for a random generator and a method for regulating the operation of this circuit, constructed from a flip-flop (P), whose inputs and output (D, C, Q) constitute the inputs and output of the metastability circuit (i1-UM, i2-UM, o-UM). The essence of the metastability circuit is a special flip-flop design with delay circuits in both the master and slave stages and a series of inputs (lo1M, lo2M, lo1S, lo2S, lsM, lsS) enabling control of the flip-flop's operation, which is controlled by a compensation and regulation circuit (UKR), also connected to the flip-flop's inputs and output (D, C, Q). The solution involves: regulating the operation between the master and slave stages of the flip-flop, adjustable slowing down of the master and slave parts over a wide range, symmetrizing the operation of each stage of the flip-flop, calibrating the metastability circuit, compensation during operation, and regulating the power consumption. It is possible to compensate for technological variations, change the position and size of the metastability window, set and adjust the flip-flop regeneration time, compensate for the effects of aging and mechanical work, or the impact of environmental factors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PL450809A PL450809A3 (en) | 2024-12-27 | 2024-12-27 | Random generator with metastability circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PL450809A PL450809A3 (en) | 2024-12-27 | 2024-12-27 | Random generator with metastability circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| PL450809A3 true PL450809A3 (en) | 2026-04-13 |
Family
ID=99397057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PL450809A PL450809A3 (en) | 2024-12-27 | 2024-12-27 | Random generator with metastability circuit |
Country Status (1)
| Country | Link |
|---|---|
| PL (1) | PL450809A3 (en) |
-
2024
- 2024-12-27 PL PL450809A patent/PL450809A3/en unknown
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