RU2000601C1 - Data input device - Google Patents

Abstract

Usage: in devices for inputting information, in particular in a digital telephone. SUBSTANCE: device contains a keyboard, four triggers, three countable triggers, five elements NOT, three AND-OR elements, two AND elements, seven OR-NOT elements, two AND-NOT elements, keyboard code generator, frequency divider, register. 3 ill.

Description

The invention relates to computing and may find application in a digital telephone.

A device for inputting information is known, comprising a keyboard connected via a code signal converter to the output bus.

A disadvantage of the known information input device is the considerable complexity of its design.

Closest to the proposed technical essence is a device for inputting information comprising a keyboard, triggers, OR-NOT elements, NAND elements, NOT elements, matching pulse shapers, an output bus, an input bus of an operating mode, an input bus of clock pulses, an input initial setup bus and setup bus zero.

It is an object of the invention to increase the reliability of information transfer by enabling multiple transmission of a pressed button code.

Figure 1 presents a diagram of a device for entering information: figure 2 - one

from options for building a keyboard; in Fig.Z - temporary aperture of the device when a button is pressed.

The device for entering information contains (Fig. 1) a keyboard 1, a first, second, third triggers 2,3,4, a second counting trigger 5, a fourth trigger 6, a first and third counting triggers 7 and 8, a first, second, fourth, third elements OR NOT 9, 10. 11, 12. element OR NOT 13, sixth and fifth elements OR NOT 14 and 15, element, second element NOT 17, element 18, the first element NOT 19, first, second and third AND-OR elements 20.21 and 22. Elements NOT 23, 24, 25. 26. 27, keyboard driver 28, frequency divider 29, matching amplifiers 30, 31, 32. 33, 34, 35, 36 and 37, output bus 38, input 39 in selection of the operating mode, clock input 40, input 41 of the initial installation and input 42 of the installation of zero. On elements 2, 3. 4, 6, 16 20, 21, 22, 23, 26 register 43 is made

The matching amplifiers 34, 35 36, 37 are made with three output states. The matching amplifiers 30 31 32 33

are complete in Htt6 (3tpff vC resistor; before setting naccWmbro, the signal level at the High level is turned off.

Figure 1 also shows the inputs and outputs of the keyboard 1-44,45,46.47.48,49,50.51.

A device for inputting information operates as follows.

The input bus 40 clock pulses continuously receive pulses with a frequency F. When you establish a logical level O on the input bus 39 of the operating mode, these pulses are fed through the elements OR NOT 13 and the element NOT 27 to the counter, collected on the counting triggers 7, 5 and 8. From the direct and inverse outputs of the counting trigger 5, pulses with a frequency of F / 4 are supplied to the seventh and sixth matching amplifiers 34 and 37, respectively. From the direct output of the counting trigger 7 and from the direct output of the counting trigger 5, the pulses arrive at the OR-NOT 15 element from which the generated signal with a frequency of F / 4 is fed to the eighth matching amplifier 36. From the direct output of the counting trigger 7 and the inverse output of the counting trigger 5 through the OR-NOT 14 element, the generated pulses with a frequency of F / 4 are fed to the fifth matching amplifier 35. From the seventh , eighth and sixth matching amplifiers 34, 35, 36 and 37, the pulses are fed to the input buses 45, 46, 47 and 44 of the keyboard 1.

By pressing a button on the keyboard 1, one of the signals present on the input buses 44, 45, 46 and 47 of the keyboard 1 is switched to the output buses 48, 49, 50 and 51 of the keyboard. From the output buses 48, 49, 50, and 51 of the keyboard, signals are sent to the first, second, third, and fourth shapers 30, 31, 32, and 33, depending on the button pressed. A pressed button signal is generated on register 43 with parallel recording and sequential reading.

The operating mode is carried out by the level of logical O coming from the output of the OR-NOT 11 element to the inputs of the first, second and third AND-OR elements 20, 21 and 22 and the AND element 16. Information for recording goes to the third inputs of these elements from the direct output counting trigger 5, from the second element OR NOT 10, from the first element OR NOT 9, as well as from the inverse output of the counting trigger 7 through the element 24.

When different buttons are pressed, different pulse sequences are received from the output buses 44, 45, 46, 47 specifically for each button. These sequences differ in pulse duration and delay relative to the input clock.

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frequency on the bus 40. cut the element OR-NOT by the sequence from Trigger 8 and form the output sequence of the element OR-NOT 11 to write to the elements AND 16, AND-OR 20. 21, 22 for triggers 2, 3, 4, 6. Gates pulses are generated on the AND-NOT element 17. The number of pulses depends on the duration of the pulses at the output of the OR-NOT element 12. The OR-NOT elements 9 and 10 generate information about the higher bits of the generated code, and the information about the lower bits is generated by the combination of pulses from the triggers 7 and 5. Thus, for each button pressed, corresponds to the specific combination supplied by the output bus 38.

The sequential read mode is carried out when logical level 1 arrives from the fourth OR-NOT element 11 to the fourth inputs of the first, second and third AND-OR elements 20. 21, 22 and AND element 16. In this mode, information is sequentially transmitted to the output bus 38 through the first, second, third and fourth triggers 2, 3, 4 and 6, to the synchronization inputs of which pulses are received respectively from the second AND-NOT element 17 and from the HE element 26. Installing the first, second, third and fourth triggers 2, 3 4 and 6 are carried out ignalom logical 1 on the bus 41 of the initial installation.

The write-read mode signal is generated on the OR-NOT 11 element, the input of which receives a signal from the third OR-NOT element and a signal from the direct output of the counting trigger 8 with a frequency of F / 8.

The signal for synchronizing the first, second, third and fourth triggers 2, 3, 4 and 6 comes from the second AND-NOT 17 element, the inputs of which receive the signal from the first AND-NOT 19 element and its clock pulses, which are fed through the input bus 40 clock pulses through the element NOT 25. The first element AND-NOT 19 receives a signal with a frequency of F / 8 and the signal from the third element OR-NOT 12 about the pressed button. The third element OR NOT 12 passes the signal of the pressed button, coming directly from the second, third and fourth matching amplifiers 31, 32, 33 pulses and from the first matching amplifier through the element And 18.

Figure 2 shows a diagram of the keyboard 1 and its connection. The input bus 46 of the keyboard is connected to the first output of the buttons 2, 6. O. D The input bus 41 of the keyboard

connected to the first output of buttons 3, 7, A. E, input bus 44 of the keyboard - with the first output of buttons 1, 5, 9, C, input bus 45 - with the first output of buttons 4.8, B. Output bus 51 of keyboard 1 is connected with the second outputs of the buttons 4, 5, 6, 7, the output bus 49 - with the second outputs of the buttons 8, 9, O, A, the output bus 48 - with the second outputs of the buttons B, C. D, E.

Claims (1)

SUMMARY OF THE INVENTION A device for inputting information, comprising a keyboard code generator, a register, an AND element, the first input of which is connected to a first output of the keyboard code generator, characterized in that, in order to increase the reliability of information transmission by making it possible to repeatedly transmit the pressed button code to six OR-NOT elements, the first and second AND-NOT elements, a frequency divider containing three NOT elements, OR-NOT elements, three countable triggers, the first input of the OR-N element introduced is the input of selecting the operating mode of the device, the second input of the OR-NOT element and the input of the first element are NOT the device clock input, the reset inputs of the counting triggers are the device zero setting input, the output of the OR-NOT element is connected to the input of the second NOT element, the output of which connected to the first clock input of the first counting trigger, the second clock input of which is connected to the output of the OR-NOT element, the inverse output of the first counting trigger is connected to the input of the third element and the first clock input of the second counting trigger, the second clock input of which is connected to the direct output of the first counting trigger, the inverse output of the second counting trigger is connected to the first clock input of the third counting trigger, the second clock input of which is connected to the direct output of the second counting trigger, the second output of the keyboard code generator the first inputs of the first, second and third elements OR NOT, the third output is connected to the second inputs of the second and third elements OR NOT, and the fourth output is connected to the second input of the first element AND NOT, and the third input of the third OR-NOT element, the output of the AND element is connected to the fourth input of the third OR-NOT element, the output of which is connected to the first inputs of the fourth OR-NOT element and the first AND-NOT element, the output of which is connected to the first input of the second the AND-NOT element, whose urpe is connected to the output of the first. element is NOT a frequency divider, the second inputs of the fourth OR-NOT element and the first I-5 element are NOT connected respectively to the direct and inverse outputs of the third counting trigger of the frequency divider, the direct output of the second the count of this trigger, the frequency divider is connected to the first input of the generator 0 of the keyboard codes and the first input of the fifth element OR-NOT. the output of which is connected to the second input of the keyboard code generator, the third input of which is connected to the output of the sixth OR-NOT element, the first 5 input of which and the fourth input of the keyboard generator are connected to the inverse output of the second counting trigger of the frequency divider, the second inputs of the sixth element OR -NOT connected to the direct output of the first counting trigger of the frequency divider, the register contains four triggers, three AND-OR elements. AND element, two NOT elements, trigger reset inputs are the input of the device’s initial installation, the output of the AND element is connected to the information input of the first trigger, the output of which is connected to the first input of the first AND-OR element, the output of which is connected to the information input of the second trigger, the output of which is connected to the first input of the second AND-OR element, the output of which is connected to the information input of the third trigger, the output of which is connected to the first input of the third 5 of the AND-OR element, the output of which is connected to the information input of the fourth trigger, the output of which is the output of the device, the output of the first element is NOT connected to the first clock inputs 0 triggers, the output of the second element is NOT connected to the second inputs of the AND-OR elements, the output of the second element is NOT connected to the second clock inputs of the triggers and the input of the first element 5 register, the output of the second OR-NOT element is connected to the third input of the third AND-OR register element, the output of the first OR-NOT is connected to the third input of the second AND-OR register element, direct 0 the output of the second counting trigger of the frequency divider is connected to the third input of the first AND-OR register element, the output of the fourth OR-NOT element is connected to the fourth inputs of the AND-OR element, input 5 of the second element NOT and the first input of the AND element of the register, the second input of the AND element of the register is connected to the output of the third element NOT of the frequency divider, the second input of the AND element is the initial setting input of the device. 1090002 44 and . 30WC6 LLL ffttfattcr uwp .. Eagn / sl. / U. Editor T. Yurchikova Compiled by V. Prokhorov Tehred M. Morgenthal $ 1 fifty 48 P # e. 2 /Mind. Proofreader V. Petrash