SE0200297L - Method for arranging silicon structures on top of each other and apparatus therefor - Google Patents

Method for arranging silicon structures on top of each other and apparatus therefor

Info

Publication number
SE0200297L
SE0200297L SE0200297A SE0200297A SE0200297L SE 0200297 L SE0200297 L SE 0200297L SE 0200297 A SE0200297 A SE 0200297A SE 0200297 A SE0200297 A SE 0200297A SE 0200297 L SE0200297 L SE 0200297L
Authority
SE
Sweden
Prior art keywords
silicon structures
apparatus therefor
intermediate layer
arranging silicon
silicon
Prior art date
Application number
SE0200297A
Other languages
Swedish (sv)
Other versions
SE0200297D0 (en
Inventor
Bjoern Ekstroem
Original Assignee
Strand Interconnect Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Strand Interconnect Ab filed Critical Strand Interconnect Ab
Priority to SE0200297A priority Critical patent/SE0200297L/en
Publication of SE0200297D0 publication Critical patent/SE0200297D0/en
Priority to PCT/SE2003/000119 priority patent/WO2003065440A1/en
Publication of SE0200297L publication Critical patent/SE0200297L/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H10W70/24—Conductive package substrates serving as an interconnection, e.g. metal plates characterised by materials
    • H10W70/26—Semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H01L21/48—
    • H01L23/4926—
    • H01L25/043—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

A method of superposing silicon structures with an intermediate layer between two mutually adjacent silicon structures. The invention is characterised by using a silicon substrate as the intermediate layer (2) and by providing the silicon substrate with a conductor pattern (1) and by connecting the silicon substrates (3, 6) on both sides of an intermediate layer (2) to the conductor pattern (1) on the intermediate layer (2).
SE0200297A 2002-02-01 2002-02-01 Method for arranging silicon structures on top of each other and apparatus therefor SE0200297L (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
SE0200297A SE0200297L (en) 2002-02-01 2002-02-01 Method for arranging silicon structures on top of each other and apparatus therefor
PCT/SE2003/000119 WO2003065440A1 (en) 2002-02-01 2003-01-23 Method to arrange silicon structures on top of each other and arrangement herefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE0200297A SE0200297L (en) 2002-02-01 2002-02-01 Method for arranging silicon structures on top of each other and apparatus therefor

Publications (2)

Publication Number Publication Date
SE0200297D0 SE0200297D0 (en) 2002-02-01
SE0200297L true SE0200297L (en) 2003-08-02

Family

ID=20286840

Family Applications (1)

Application Number Title Priority Date Filing Date
SE0200297A SE0200297L (en) 2002-02-01 2002-02-01 Method for arranging silicon structures on top of each other and apparatus therefor

Country Status (2)

Country Link
SE (1) SE0200297L (en)
WO (1) WO2003065440A1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268381A (en) * 1993-03-11 1994-09-22 Hitachi Ltd Multilayer wiring structure and its manufacture
JP3563604B2 (en) * 1998-07-29 2004-09-08 株式会社東芝 Multi-chip semiconductor device and memory card
TW442873B (en) * 1999-01-14 2001-06-23 United Microelectronics Corp Three-dimension stack-type chip structure and its manufacturing method

Also Published As

Publication number Publication date
SE0200297D0 (en) 2002-02-01
WO2003065440A1 (en) 2003-08-07

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Legal Events

Date Code Title Description
NAV Patent application has lapsed